Pi2EQX5804DNJE Pericom Semiconductor, Pi2EQX5804DNJE Datasheet - Page 12

• Manufacturer Part Number: Pi2EQX5804DNJE
• Description: Buffers & Line Drivers
• Manufacturer: Pericom Semiconductor

Specifications of Pi2EQX5804DNJE

• Logic Family: PI2EQX5804
• Logic Type: Serial Re-Driver
• Supply Voltage (max): 2.5 V
• Supply Voltage (min): - 0.5 V
• Maximum Operating Temperature: + 70 C
• Data Rate: 5 Gbps
• Maximum Power Dissipation: 1 W
• Minimum Operating Temperature: 0 C
• Output Current: +/- 25 mA
• Output Voltage: 0.4 V
• Supply Current: 800 mA

BYTE 3 - Channel Input Disable (INDIS)
INDIS_xy=0=enable input, INDIS_xy=1=disable input
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Input Disable register, provides control over the input buffer of each channel independently.
When and INDIS_xy bit is logic 1, then the input buffer is switched off and the input termination is high im-
pedance. This feature can be used for PCB testing, and when only one input is used during Loopback as a de-
mux function. When INDIS_xy is at a logic 0 state then the input buffer is enabled (normal operating mode).
BYTE 4 - Channel Output Disable (OUTDIS)
ODIS_xy=0=enable output, ODIS_xy=1=disable output
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Output Disable register, allows control over the output buffer of each channel independently.
When and OUTDIS_xy bit is logic 1, then the output buffer is switched off and the termination is high imped-
ance. This feature can be used for PCB testing, and when only one output is used during Loopback as a mux
function. When INDIS_xy is at a logic 0 state then the input buffer is enabled (normal operating mode).
BYTE 5 - Channel Reset (RESET)
RES_xy# =0=reset, RES_xy# =1=normal operation. Latch from RESET# input at startup
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undefined, rsvd=reserved for future use
The Channel Reset register allows for restart of an individual channels Receiver Detect function. A transition
from 0 to 1 initiates a new Receiver Detect cycle (if the channel is enabled and receiver detect is enabled).
While static at 0 or 1, the RES_zy# bit will have no effect on operation. The Channel Reset bits are read/write
allowing the current state to be checked.
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Power-on
Power-on
Power-on
Name
Name
Name
Type
State
Type
State
Type
State
Bit
Bit
Bit
INDIS_A0
ODIS_A0
RES_A0#
RESET#
R/W
R/W
R/W
7
0
7
0
7
INDIS_B0
ODIS_B0
RES_B0#
RESET#
R/W
R/W
R/W
6
0
6
0
6
INDIS_A1
ODIS_A1
RES_A1#
RESET#
5.0Gbps 4-Lane PCIe® 2.0 ReDriver™ with Equalization & Emphasis
R/W
R/W
R/W
5
0
5
0
5
INDIS_B1
ODIS_B1
RES_B1#
RESET#
R/W
R/W
R/W
12
4
0
4
0
4
10-0170
INDIS_A2
ODIS_A2
RES_A2#
RESET#
R/W
R/W
R/W
0
3
0
3
3
INDIS_B2
ODIS_B2
RES_B2#
RESET#
R/W
R/W
R/W
2
0
2
0
2
www.pericom.com
INDIS_A3
ODIS_A3
RES_A3#
RESET#
PI2EQX5804D
R/W
R/W
R/W
1
0
1
0
1
P-0.1
INDIS_B3
ODIS_B3
RES_B3#
RESET#
R/W
R/W
R/W
0
0
0
0
0
05/28/10