M95160-WMN3TP/S STMicroelectronics, M95160-WMN3TP/S Datasheet - Page 47

• Manufacturer Part Number: M95160-WMN3TP/S
• Manufacturer: STMicroelectronics

Specifications of M95160-WMN3TP/S

• Density: 16Kb
• Interface Type: Serial (SPI)
• Organization: 2Kx8
• Access Time (max): 60ns
• Frequency (max): 5MHz
• Write Protection: Yes
• Data Retention: 40Year
• Operating Supply Voltage (typ): 3.3/5V
• Operating Temp Range: -40C to 125C
• Supply Current: 2mA
• Operating Supply Voltage (min): 2.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Automotive
• Mounting: Surface Mount
• Pin Count: 8
• Lead Free Status / Rohs Status: Compliant

M95160-x, M95080-x
12
Revision history
Table 35.
06-Feb-2002
04-Nov-2002
13-Nov-2002
21-Nov-2003
21-Sep-2005
18-Oct-2002
08-Jun-2004
07-Oct-2004
19-Jul-2001
Date
Document revision history
Revision
1.0
1.1
1.2
1.3
1.4
2.0
3.0
4.0
5.0
Announcement made of planned upgrade to 10MHz clock for the 5V, –40
to 85°C, range
TSSOP8 (3x3mm body size, MSOP8) package added
New products, identified by the process letter W, added
Correction to footnote in Ordering Information table
Table of contents, and Pb-free options added. V
0.45V
MLP8 package added. Absolute Maximum Ratings for V
V
compliant devices. Device Grade 3 clarified, with reference to HRCF and
automotive environments. Process identification letter “G” information
added. SO8 narrow and TSSOP8 Package mechanical specifications
updated.
Product List summary table added. AEC-Q100-002 compliance. tHHQX
corrected to tHHQV.
10MHz, 5ms Write is now the present product. tCH+tCL<1/fC constraint
clarified
Added 20MHz and -S product information. Removed DIP package. Info on
Pull-up resistors, VCC lines and Note
and memory devices on the SPI
clarified. Packages compliant with the JEDEC Std J-STD-020C. Process
info updated in
information
Document written from previous M95640/320/160/080 datasheet
CC
(min) improved. Soldering temperature information clarified for RoHS
Doc ID 8028 Rev 10
scheme.
DC and AC parameters
Changes
bus.
Device internal reset
2.
and
added to
Table 32.: Ordering
IL
(min) improved to –
Figure 4.: Bus master
Revision history
IO
(min) and
paragraph
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