ZLF645E0P2832G Zilog, ZLF645E0P2832G Datasheet - Page 124

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ZLF645E0P2832G

Manufacturer Part Number
ZLF645E0P2832G
Description
Microcontrollers (MCU) 32K Flash 1K RAM 28 pin
Manufacturer
Zilog
Datasheet

Specifications of ZLF645E0P2832G

Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
32 KB
Data Ram Size
1 KB
Interface Type
ICP, UART
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
Through Hole
Package / Case
PDIP-28
Minimum Operating Temperature
0 C
Lead Free Status / Rohs Status
 Details
PS026407-0408
Bit Position
[5:4]
[3:2]
Value
00
01
10
00
01
10
00
01
10
00
01
10
11
11
11
11
Description
TRANSMIT Mode
T8/T16 Logic—Defines how the Timer 8/Timer 16 outputs are combined logically.
These bits are not reset upon Stop Mode Recovery.
Output is T8 AND T16.
Output is T8 OR T16.
Output is T8 NOR T16.
Output is T8 NAND T16.
DEMODULATION Mode
Edge Detect—Define the behavior of the edge detector.
Falling edge detection.
Rising edge detection.
Falling and rising edge detection.
Reserved.
TRANSMIT Mode
Submode Selection—Select NORMAL or PING-PONG mode operation, or force
T16 output. When these bits are written to 00b (NORMAL mode) or 01b
(PING-PONG mode), T16_OUT assumes the opposite state of bit CTR1[0] until
the timer begins counting.
Normal operation. Writing 00 terminates PING-PONG mode, if it is active.
PING-PONG mode.
Force T16_OUT = 0
Force T16_OUT = 1
DEMODULATION Mode
Glitch Filter—Define the maximum glitch width to be rejected by the
counter/timer.
No filter.
4 SCLK cycle filter.
8 SCLK cycle filter.
Reserved.
ZLF645 Series Flash MCUs
Product Specification
Counter/Timer Registers
116

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