STM32L152C8U6 STMicroelectronics, STM32L152C8U6 Datasheet - Page 80
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STM32L152C8U6
Manufacturer Part Number
STM32L152C8U6
Description
Microcontrollers (MCU) 32-Bit Arm Cortex M3 64kb LCD Ultralow
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32L152-EVAL.pdf
(107 pages)
Specifications of STM32L152C8U6
Core
ARM Cortex M3
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
32MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
37
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 16x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-UFQFN Exposed Pad
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32L152C8U6
Manufacturer:
STM
Quantity:
200
Company:
Part Number:
STM32L152C8U6
Manufacturer:
STMicroelectronics
Quantity:
10 000
Electrical characteristics
80/107
SPI characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under ambient temperature, f
conditions summarized in
Refer to
function characteristics (NSS, SCK, MOSI, MISO).
Table 44.
1. Remapped SPI1 characteristics to be determined.
2. Based on characterization, not tested in production.
3. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the
4. Min time is for the minimum time to invalidate the output and max time is for the maximum time to put the
DuCy(SCK)
t
t
t
t
t
t
dis(SO)
t
w(SCKH)
v(SO)
t
w(SCKL)
v(MO)
su(NSS)
t
a(SO)
Symbol
1/t
t
data.
data in Hi-Z.
t
t
h(NSS)
t
su(MI)
t
h(MO)
su(SI)
h(MI)
h(SO)
t
t
h(SI)
r(SCK)
f(SCK)
f
c(SCK)
SCK
(2)(3)
(2)(1)
(2)(1)
(2)
(2)(4)
(2)
(2)
(2)
(2)
Section 6.3.11: I/O port characteristics
(2)
(2)
(2)
(2)
(2)
SPI characteristics
SPI clock frequency
SPI clock rise and fall
time
SPI slave input clock duty
cycle
NSS setup time
NSS hold time
SCK high and low time
Data input setup time
Data input hold time
Data output access time
Data output disable time
Data output valid time
Data output valid time
Data output hold time
Parameter
Table
Doc ID 17659 Rev 4
9.
(1)
Master mode
Slave mode
Capacitive load: C = 30 pF
Slave mode
Slave mode
Slave mode
Master mode, f
presc = 4
Master mode
Slave mode
Master mode
Slave mode
Slave mode, f
Slave mode
Slave mode (after enable edge)
Master mode (after enable edge)
Slave mode (after enable edge)
Master mode (after enable edge)
PCLKx
for more details on the input/output alternate
Conditions
PCLK
frequency and V
PCLK
= 20 MHz
= 16 MHz,
STM32L151xx, STM32L152xx
DD
4t
2t
Min
TBD
TBD
TBD
TBD
supply voltage
PCLK
PCLK
30
5
5
5
4
0
3t
Max
TBD
TBD
TBD
TBD
TBD
PCLK
16
16
70
MHz
Unit
ns
ns
%