SST89C58RC-40-I-QIF Microchip Technology, SST89C58RC-40-I-QIF Datasheet
SST89C58RC-40-I-QIF
Specifications of SST89C58RC-40-I-QIF
Related parts for SST89C58RC-40-I-QIF
SST89C58RC-40-I-QIF Summary of contents
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... Full-Duplex, Enhanced UART – Framing error detection – Automatic address recognition PRODUCT DESCRIPTION The SST89C58RC is a member of the FlashFlex family of 8-bit micro controllers designed and manufactured with SST patented and proprietary SuperFlash CMOS semi- conductor process technology. The split-gate cell design and thick-oxide tunneling injector offer significant cost and reliability benefits for customers ...
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... Power Saving Considerations for Using the Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 8.0 SECURITY LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.1 Chip-Level Security Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.2 Page-Level Security Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 8.3 Read Operation Under Lock Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 9.0 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.1 Power-on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.2 Interrupt Priority and Polling Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ©2008 Silicon Storage Technology, Inc. 2 FlashFlex MCU SST89C58RC S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC 10.0 POWER-SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.1 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.2 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 11.0 SYSTEM CLOCK AND CLOCK OPTIONS 11.1 Clock Input Options and Recommended Capacitor Values for Oscillator . . . . . . . . . . . . . . . . . . . . . . 63 11.2 Clock Doubling Option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 12.0 ELECTRICAL SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 12.1 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 12.2 AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 13 ...
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... Test Condition, Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DD FIGURE 12-10: I Test Condition, Power-down Mode FIGURE 14-1: 44-lead Plastic Lead Chip Carrier (PLCC FIGURE 14-2: 44-lead Thin Quad Flat Pack (TQFP FIGURE 14-3: 40-Contact Very-Very-Thin Quad Flat No-lead (WQFN ©2008 Silicon Storage Technology, Inc. 4 FlashFlex MCU SST89C58RC S71323-02-000 02/08 ...
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... TABLE 12-3: AC Conditions of Test TABLE 12-4: Recommended System Power-up Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TABLE 12-5: Pin Impedance (VDD=3.3V, TA=25 °C, f=1 Mhz, other pins open TABLE 12-6: DC Characteristics for SST89C58RC TABLE 12-7: AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 TABLE 12-8: Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 TABLE 12-9: Flash Memory Programming/Verification Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 TABLE 14-1: Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 © ...
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... B-Register, Instruction Register, Program Counter, Timing and Control Interrupt Control Flash Control Unit RAM 1K x8 I/O Port 0 Security I/O Port 1 Lock I/O Port 2 I/O Port 3 BOR 8-bit Enhanced UART 6 FlashFlex MCU SST89C58RC 9 Interrupts 8 I I/O 8 I/O 8 I/O 1323 B1.0 S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC 2.0 PIN ASSIGNMENTS (SDA1) P1.5 (SDA0) P1.6 (SCL0) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0#) P3.2 (INT1#) P3.3 (T0) P3.4 ( T1) P3.5 FIGURE 2-1: Pin Assignments for 44-Lead TQFP (SDA1) P1.5 (SDA0) P1.6 (SCL0) P1.7 RST (RXD) P3.0 NC (TXD) P3.1 (INT0#) P3 ...
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... P3.4 (T1) P3.5 FIGURE 2-3: Pin Assignments for 40-Contact WQFN ©2008 Silicon Storage Technology, Inc Top View (contacts facing down) 8 FlashFlex MCU SST89C58RC P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA# ALE/PROG# PSEN# P2.7 (A15) P2.6 (A14) P2.5 (A13) 1323 40-wqfn QI P3.0 ...
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... FlashFlex MCU SST89C58RC 2.1 Pin Descriptions TABLE 2-1: Pin Descriptions ( Symbol Type Name and Functions P0[7:0] I/O Port 0: Port 8-bit open drain bi-directional I/O port output port each pin can sink several LS TTL inputs. Port 0 pins that have ‘1’s written to them float, and in this state can be used as high-impedance inputs ...
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... VDD which consumes extra power. ©2008 Silicon Storage Technology, Inc emitted at a constant rate of 1/6 the crystal frequency , e.g. for ALE pin FlashFlex MCU SST89C58RC 3 . One T2-1.0 1323 S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC 3.0 MEMORY ORGANIZATION The SST89C58RC has separate address spaces for pro- gram and data memory. 3.1 Program Flash Memory There are two internal flash memory partitions in the device. The primary flash memory partition (Partition 0) has 32 KByte. The secondary flash memory partition (Partition 1) has 2 KByte ...
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... The RAM can be addressed KByte for exter- nal data memory. 3.3 Expanded Data RAM Addressing The SST89C58RC has the capability of 1 KByte of RAM. See Figure 3-2. The device has four sections of internal data memory: 1. The lower 128 Bytes of RAM (00H to 7FH) are directly and indirectly addressable ...
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... FlashFlex MCU SST89C58RC TABLE 3-1: External Data Memory RD#, WR# with EXTRAM bit MOVX @DPTR MOVX A, @DPTR AUXR ADDR < 0300H EXTRAM = 0 RD# / WR# not asserted EXTRAM = 1 RD# / WR# asserted 1. Access limited to ERAM address within 0 to 0FFH. 100H to 02FFH is not accessible. 2FFH Expanded RAM 768 Bytes ...
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... Preliminary Specification 3.4 Dual Data Pointers The SST89C58RC has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS=0, DPTR0 is selected; when DPS=1, DPTR1 is selected. Quickly switching between the two data pointers can be accom- plished by a single INC instruction on AUXR1 ...
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... FlashFlex MCU SST89C58RC TABLE 3-2: FlashFlex SFR Memory Map F8H F0H B E8H IEN1 E0H ACC D8H SM0CON0 D0H PSW SM1CON0 C8H T2CON T2MOD C0H WDTC B8H IP0 S0ADEN B0H P3 SFCF A8H IEN0 SADDR A0H P2 PMC 98H S0CON S0BUF 90H P1 IP1 88H ...
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... From From- Clock- Extern- Zero User- Double Host- Vector Cmd Bit Address, Symbol, or Alternative Port Function MSB - WDTON WDFE - Watchdog Timer Data/Reload 16 FlashFlex MCU SST89C58RC Reset LSB Value - SFST_SEL 01x0x000b x0000000b BFH PAGE2 PAGE1 PAGE0 xxx11111b Disable- Disable- Disable- x1111111b Extern- ...
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... FlashFlex MCU SST89C58RC TABLE 3-6: Timer/Counter SFR Direct Symbol Description Address TMOD Timer/Counter 89H Mode Control 1 TCON Timer/Counter 88H Control TH0 Timer 0 MSB 8CH TL0 Timer 0 LSB 8AH TH1 8DH Timer 1 MSB TL1 Timer 1 LSB 8BH 1 T2CON Timer/Counter 2 C8H Control T2MOD# ...
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... P0[7:0] RD# WR Bit Address, Symbol, or Alternative Port Function MSB (Write only) (Write only) Bit Address, Symbol, or Alternative Port Function Direct Address MSB BFH - - - - 18 FlashFlex MCU SST89C58RC LSB TB8 RB8 TI RI AA_0 FTE_0 TOE_0 CRSEL_0 GC_0 PWRU PWR STADY EXHOLD_0 P_SI0 UP_E ...
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... FlashFlex MCU SST89C58RC SuperFlash Configuration Register (SFCF) Location 7 6 B1H CMD_ IAPEN Status Symbol Function CMD_Status IAP Command Completion Status 0: IAP command is ignored 1: IAP command is completed fully IAPEN IAP Enable Bit 0: Disable all IAP commands (Commands will be ignored) 1: Enable all IAP commands ...
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... SFAH=B1H; Disable-Extern-Boot SFAH=B2H; Disable-Extern-MOVC SFAH=B3H; Disable-Extern-Host-Cmd Boot Option Setting Commands SFAH=E0H; Enable-Clock-Double SFAH=E1H; Prog-Boot-Default SFAH=E2H; Prog-Boot-Jumper SuperFlash Low Order Byte Address Register SuperFlash High Order Byte Address Register 20 FlashFlex MCU SST89C58RC Reset Value FCM2 FCM1 FCM0 x0000000b Reset Value Reset Value ...
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... FlashFlex MCU SST89C58RC SuperFlash Data Register (SFDT) Location 7 6 B5H Symbol Function SFDT Mailbox register for interfacing with flash memory block. (Data register) SuperFlash Status Register (SFST) (Read Only Register) Location 7 6 B6H Symbol Function SFST This is a read-only register. The read-back value is indexed by SFST_SEL in the SuperFlash Configuration Register (SFCF) SFST_SEL=0H: Manufacturer’ ...
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... SMBus 0 Interrupt priority bit high ©2008 Silicon Storage Technology, Inc PT2 PS0 PT1 PX1 PT2H PS0H PT1H PX1H FlashFlex MCU SST89C58RC Reset Value PT0 PX0 xx000000b Reset Value PT0H PX0H xx000000b Reset Value - PM1 PM0 x0xxxx00b Reset Value - PM1H PM0H x0xxx00b ...
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... FlashFlex MCU SST89C58RC Auxiliary Register (AUXR) Location 7 6 8EH - - Symbol Function EXTRAM Internal/External RAM access 0: Internal Expanded RAM access within range of 00H to FFH using MOVX @Ri / @DPTR. Beyond 100H, the MCU always accesses external data memory For details, refer to Section 3.3, “Expanded Data RAM Addressing” ...
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... Software sets the bit to force a Watchdog timer refresh. SWDT Start Watchdog timer. 0: Stop WDT. 1: Start WDT. Watchdog Timer Data/Reload Register (WDTD) Location 7 6 85H ©2008 Silicon Storage Technology, Inc WDFE - WDRE WDTS Watchdog Timer Data/Reload 24 FlashFlex MCU SST89C58RC Reset Value WDT SWDT x00x0000b Reset Value 00H S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC Clock Option Register (COSR) Location 7 6 BFH - - Symbol Function COEN Clock Divider Enable 0: Disable Clock Divider 1: Enable Clock Divider CO_SEL Clock Divider Selection 00b: 1/4 clock source 01b: 1/16 clock source 10b: 1/256 clock source 11b: 1/1024 clock source ...
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... SCL Low timeout disabled 1: SCL Low timeout enabled CRSEL_0 SCL Clock Source Selection 0: SMBus internal baud generator generates the SCL 1: TIMER1 overflow generates the SCL ©2008 Silicon Storage Technology, Inc STO_0 SI_0 AA_0 FTE_0 26 FlashFlex MCU SST89C58RC Reset Value TOE_0 CRSEL_0 00H S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC SMBus0 Control Register1 (SM0CON1) Location DFH Symbol Function PWRUP_SI0 Power-down Wakeup Flag - When the SUBus wakes up the MCU, the flag bit is set by hardware. The bit is in ready-only mode. Only writing ‘0’ to this bit will clear the flag. If SMBus interrupt enable bit is set, then the SMBus interrupt is generated when the flag bit is ‘ ...
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... Location 7 6 D3H ©2008 Silicon Storage Technology, Inc PWRUP_SI1 PWRUP_EN1 STADY_1 SM0DAT[7: SM1DAT[7:0] 28 FlashFlex MCU SST89C58RC 1 0 Reset Value EXTHOLD_1 F0H 1 0 Reset Value 0 0 F8H 1 0 Reset Value 0 0 F8H 1 0 Reset Value 00H 1 0 Reset Value 00H S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC SMBus01 Address Register 0 (SM0ADR) Location 7 6 D4H SMBus1 Address Register 1 (SM1ADR) Location 7 6 D4H SMBus0 High-Duty Setting Register (SM0SCLH) Location 7 6 DDH Symbol Function SM0SCLH[7:0] Set the SCL high duration SMBus0 Low-Duty Setting Register (SM0SCLL) Location 7 6 DEH ...
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... Activates Power-down mode. IDL Idle mode bit, this bit is cleared by hardware after exiting from idle mode. 0: Idle mode is not activated. 1: Activates idle mode. ©2008 Silicon Storage Technology, Inc POF GF1 GF0 30 FlashFlex MCU SST89C58RC 1 0 Reset Value PD IDL 00x10000b S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC Serial Port Control Register (S0CON) Location 7 6 98H SM0/FE SM1 Symbol Function FE Set SMOD0 = 1 to access FE bit framing error 1: Framing Error. Set by receiver when an invalid stop bit is detected. This bit needs to be cleared by software. SM0 SMOD0 = 0 to access SM0 bit. ...
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... Timer 2 Output Enable bit. DCEN Down Count Enable bit. When set, this allows Timer configured as an up/down counter. ©2008 Silicon Storage Technology, Inc RCLK TCLK EXEN2 FlashFlex MCU SST89C58RC Reset Value TR2 C/T2# CP/RL2 Reset Value - T2OE DCEN xxxxxx00b S71323-02-000 00H 02/08 ...
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... While the flash control executes IAP commands, the CPU is on hold since there is only one physical flash block in the SST89C58RC devices. When IAP commands finish, the CPU can resume execution of the application code. So the application code needs to turn ...
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... Write FDH to SFIS1 (0C4H) 3. Then write IAP command to SFCM (0B2H) FIGURE 4-1: Chip-Erase Address 0F800H T4-4.1 1323 34 FlashFlex MCU SST89C58RC Feed Sequence T4-3.0 1323 IAP Enable ORL SFCF, #40H Set-Up MOV SFDT, #55H Feed Sequence MOV SFIS0, #A2H MOV SFIS1, #DFH ...
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... FlashFlex MCU SST89C58RC 4.2.1.2 Partition0-Erase The Partition0-Erase command erases all bytes in memory partition 0. All security bits associated with Page0-3 are also reset. IAP Enable ORL SFCF, #40H Set-Up MOV SFDT, #55H Feed Sequence MOV SFIS0, #A2H MOV SFIS1, #DFH Command Execution ...
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... IAP Enable ORL SFCF, #40H Set-up Enable-Clock-Double MOV SFAH, #E0H Feed Sequence MOV SFIS0, #A2H MOV SFIS1, #DFH Program Enable-Clock-Double Command Execution MOV SFCM, #08H SFCF[7] indicates operation complete FIGURE 4-7: Enable-Clock-Double 36 FlashFlex MCU SST89C58RC 1323 F43.0 S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC 4.3 In-System Programming The bootstrap loader (BSL) is located in partition 1 and cannot be accessed unless the SFR AUXR1 (Address = A2H), Bit 5 is enabled. The default value of this bit after reset is ‘1’ unless the “Boot-From-Zero” bit is non-zero dur- ing reset, or P1.0 and P1.1 are pulled low while EA# is held high on the falling edge of the reset ...
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... FIGURE 4-9: Hardware Enter Mode ©2008 Silicon Storage Technology, Inc. Boot status bit in the SFCF register to determine whether the latest boot was based on the hardware enter mode. See Figure 4-9. 300 Cycles 300 Cycles 1294 F62.0 38 FlashFlex MCU SST89C58RC S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC 5.0 TIMERS/COUNTERS 5.1 Timers The device has three 16-bit registers that can be used as either timers or event counters. The three timers/counters are denoted Timer 0 (T0), Timer 1 (T1), and Timer 2 (T2). Each is designated a pair of 8-bit registers in the SFRs. The pair consists of a most significant (high) byte and least significant (low) byte ...
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... After the FE bit has been set, it can only be cleared by software. Valid stop bits do not clear FE. When FE is enabled, RI rises on the stop bit, instead of the last data bit (see Figure 6-2 and Figure 6-3). 40 FlashFlex MCU SST89C58RC S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC SM0/FE SM1 SMOD1 SMOD0 FIGURE 6-1: Framing Error Block Diagram RXD D0 Start bit RI SMOD0=X FE SMOD0=1 FIGURE 6-2: UART Timings in Mode 1 RXD D0 Start bit RI SMOD0=0 RI SMOD0=1 FE SMOD0=1 FIGURE 6-3: UART Timings in Modes 2 and 3 ©2008 Silicon Storage Technology, Inc. SM2 ...
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... If the user added a third slave such as the example below: Slave 2 SADDR = 1111 0011 SADEN = 1111 1001 GIVEN = 1111 0XX1 42 FlashFlex MCU SST89C58RC Possible Addresses 1111 0000 1111 0100 Possible Addresses 1111 0111 1111 0011 Possible Addresses 1111 0001 1111 0101 Slave 3 SADDR = ...
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... FlashFlex MCU SST89C58RC Select Slave 3 Only Slave 2 Given Address Possible Addresses 1111 X0X1 The user could use the possible addresses above to select slave 3 only. Another combination could be to select slave 2 and 3 only as shown below. Select Slaves 2 and 3 Only Slaves 2 and 3 Possible Addresses ...
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... Preliminary Specification 6.2 Enhanced SMBus Interface The SST89C58RC includes two enhanced SUBus inter- faces. The enhanced SMBus uses two wires (SDA and SCL) to transfer information between devices connected to the bus. 6.2.1 SUBus Features • Only two lines required (SDA and SCL) • ...
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... FlashFlex MCU SST89C58RC 6.2.2.1 SDA (Serial Data Line) The SDA line is the SMBus serial data line, and is primarily driven by the master or slave transmitter. The SDA is changeable when SCL is low, and SDA is stable when SCL is high. Perform bus arbitration on SDA when SCL is high. ...
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... SCL and SDA lines high for more than 10 SMBus bit rate cycles. 6.4 SMBus SFR The SST89C58RC has two identical SMBus interfaces, each identical with the exception of the SFR addresses and the I/O pins associated with each interface. ...
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... FlashFlex MCU SST89C58RC 1 = When set acknowledge (low level to SDA) will be returned during the acknowledge clock pulse on the SCL line on the following situations: 3. The “own slave address” has been received. 4. The general call address has been received while the general call bit (GC) in SMBADR is set. ...
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... No SM0DAT action FlashFlex MCU SST89C58RC SMBus Hardware - Next Action AA X SLA+W transmitted; ACK bit received X SLA+W transmitted; ACK bit received X SLA+W transmitted; SMBus switched to MST/REC mode X Data byte transmitted; ACK received X Repeat START transmitted X STOP condition transmitted STO flag reset ...
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... FlashFlex MCU SST89C58RC TABLE 6-3: Master Receiver Mode Status Code SMBus Hardware Status (SM0STA) 08H START condition transmitted 10H Repeat START transmitted 38H Arbitration lost in NOT ACK bit 40H SLA+R transmitted; ACK received 48H SLA+R transmitted; NOT ACK received 50H Data byte received; ...
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... Read data byte FlashFlex MCU SST89C58RC SMBus Hardware - Next Action AA X Data byte received; NOT ACK bit returned 1 Data byte received; ACK returned 0 Data byte received; NOT ACK bit returned 1 Data byte received; ACK returned 0 Data byte received; NOT ACK bit ...
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... FlashFlex MCU SST89C58RC TABLE 6-4: Slave Receiver Mode Status Code SMBus Hardware Status (SM0STA) 98H Previously General Call addressed; DATA byte received; ACK returned A0H A STOP condition or a START condition received while addressed as SLV/REC or SLV/TRX ©2008 Silicon Storage Technology, Inc. Application Software Response ...
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... No SM0DAT action FlashFlex MCU SST89C58RC SMBus Hardware - Next Action AA 0 Last data byte transmitted; ACK received 1 Data byte transmitted; ACK received 0 Last data byte transmitted; ACK received 1 Data byte transmitted; ACK received 0 Last data byte transmitted; ACK received 1 Data byte transmitted; ACK received 0 Switch to non-addressed SLV mode ...
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... FlashFlex MCU SST89C58RC TABLE 6-6: Miscellaneous Status Status Code SMBus Hardware Status (SM0STA) F8H No available state informa- tion ‘0’ 00H Bus error during MST or selected Slave modes caused by illegal START or STOP; or SMBus entered an undefined state D0H SCL high timeout ©2008 Silicon Storage Technology, Inc. ...
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... COMPARATOR SM0DAT SHIFT REGISTER ARBITRATION & SYNC LOGIC SERIAL CLOCK GENERATOR TIMER 1 OVERFLOW SM0CON CONTROL REGISTER SM0SCLL SM0SCLH STATUS DECODER STATUS BUS SM0STA STATUS REGISTER 54 FlashFlex MCU SST89C58RC 8 SM0ADR ACK 8 TIMING & CCLK CONTROL LOGIC INTERRUPT 8 8 S71323-02-000 1323 F46.1 02/08 ...
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... FlashFlex MCU SST89C58RC 6.4.5 SMBus SCL High and Low Duty SM0SCLH sets the SCL high duration and SM0SCLL sets the SCL low duration. The SM0SCLH and SM0SCLL reg- isters must be set to select the bit rate when the internal clock source for the SMBUS SCL is selected. To select the internal serial clock source for the SM0CLL, set CRSEL = ‘ ...
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... During Power- down mode, the Watchdog timer is stopped. When the Watchdog timer is used as a pure timer, users can turn off the clock to save power. See “Power Management Control Register (PMC)” on page 25. 56 FlashFlex MCU SST89C58RC CLK (XTAL1) S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC CLK (XTAL1) Counter Ext. RST WDTC FIGURE 7-1: Block Diagram of Programmable Watchdog Timer ©2008 Silicon Storage Technology, Inc. 344064 WDT Reset clks WDT Upper Byte WDTD 57 Preliminary Specification Internal Reset 1323 F47.0 S71323-02-000 02/08 ...
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... Read Operation Under Lock Condition The following three cases can be used to indicate the Read operation is targeting a locked, secured memory area: 1. External host mode: Read-back = 55H (locked) 2. IAP command: Read-back = previous SFDT data 3. MOVC: Read-back = 00H (blank) 58 FlashFlex MCU SST89C58RC S71323-02-000 02/08 ...
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... The device supports seven interrupt sources under a four level priority scheme. Table 9-1 and Figure 9-2 summarize the polling sequence of the supported interrupts. through rise DD 59 Preliminary Specification + RST SST89C58RC C 2 XTAL2 XTAL1 C 1 1323 F48.0 9-1: Power-on Reset Circuit S71323-02-000 02/08 ...
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... INT1# IT1 1 TF1 RI TI TF2 EXF2 Individual Enables FIGURE 9-2: Interrupt Sequence ©2008 Silicon Storage Technology, Inc. IP/IPH/IPA/IPAH IE & IEA Registers Registers IE1 Global Disable 60 FlashFlex MCU SST89C58RC Highest Priority Interrupt Interrupt Polling Sequence Lowest Priority Interrup 1323 F49.0 S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC TABLE 9-1: Interrupt Table Interrupt Description Ext. Int0 SMBus0 T0 Ext. Int1 T1 UART T2 TF2, EXF2 SMBus1 Watchdog ©2008 Silicon Storage Technology, Inc. Vector Flag Address IE0 0003H - 002BH TF0 000BH IE1 0013H TF1 001BH TI/RI 0023H 003BH - 0043H - 0053H ...
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... ALE and PSEN# signals at a LOW level during power -down. • External Interrupts are only active for level sensitive interrupts, if enabled. 62 FlashFlex MCU SST89C58RC the interrupt service IH, DD Exited by Enabled interrupt or hardware reset. Start of interrupt clears IDL bit and exits idle ...
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... FlashFlex MCU SST89C58RC 11.0 SYSTEM CLOCK AND CLOCK OPTIONS 11.1 Clock Input Options and Recom- mended Capacitor Values for Oscillator Shown in Figure 11-1 are the input and output of an inter- nal inverting amplifier (XTAL1, XTAL2), which can be con- figured for use as an on-chip oscillator. ...
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... C capable in both non-Pb and with-Pb solder versions. ° C for 10 seconds; please consult the factory for the latest information. Min. 0 -40 2 Minimum Specification 10,000 100 100 + FlashFlex MCU SST89C58RC +0.5V DD +1.0V DD Max Unit ° +70 C ° + MHz 40 MHz T12-1 ...
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... FlashFlex MCU SST89C58RC TABLE 12-3: AC Conditions of Test Input Rise/Fall Time . . . . . . . . . . . . . . . 10 ns Output Load . . . . . . . . . . . . . . . . . . . . . C See Figures 12-5 and 12-7 TABLE 12-4: Recommended System Power-up Timings Symbol Parameter 1 T Power-up to Read Operation PU-READ 1 T Power-up to Write Operation PU-WRITE 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter TABLE 12-5: Pin Impedance (VDD=3.3V, TA=25 ° ...
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... Preliminary Specification 12.1 DC Electrical Characteristics TABLE 12-6: DC Characteristics for SST89C58RC: T Symbol Parameter V Operating Voltage DD V Input Low Voltage P0, P1, P2, P3, EA# IL1 V Input Low Voltage RST IL2 V Input Low Voltage XTAL IL3 Input Low Voltage P1.4/SCL1, P1.5/SDA1, V IL4 P1.6/SDA0, P1.7/SCL0 V Input High Voltage P0, P1, P2, P3, EA# ...
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... FlashFlex MCU SST89C58RC 12.2 AC Electrical Characteristics AC Characteristics: (Over Operating Conditions: Load Capacitance for Port 0, ALE, and PSEN# = 100pF; Load Capacitance for All Other Outputs = 80pF) TABLE 12-7: AC Electrical Characteristics T Symbol Parameter 1/T x1 Mode Oscillator Frequency CLCL 1/2T x2 Mode Oscillator Frequency CLCL ...
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... For example Time from Address Valid to ALE Low AVLL T = Time from ALE Low to PSEN# Low LLPL ©2008 Silicon Storage Technology, Inc. Q: Output data R: RD# signal T: Time V: Valid W: WR# signal X: No longer a valid logic level Z: High Impedance (Float) 68 FlashFlex MCU SST89C58RC S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC T LHLL ALE PSEN# PORT 0 PORT 2 FIGURE 12-1: External Program Memory Read Cycle T LHLL ALE PSEN# RD# T AVLL A0-A7 FROM RI or DPL PORT 0 PORT 2 FIGURE 12-2: External Data Memory Read Cycle ©2008 Silicon Storage Technology, Inc. T PLPH T T AVLL ...
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... T XLXL T XHQX XHDV T XHDX VALID VALID VALID VALID 70 FlashFlex MCU SST89C58RC T WHLH T WHQX A0-A7 FROM PCL INSTR IN A8-A15 FROM PCH 1323 F53.0 Oscillator Variable Min Max 12T CLCL 10T - 133 CLCL 2T - 117 CLCL CLCL 0 10T - 133 CLCL ...
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... FlashFlex MCU SST89C58RC AC Inputs during testing are driven (0.45V) for a Logic "0". Measurement reference points for inputs and ILT outputs are at V FIGURE 12-5: AC Testing Input/Output Test Waveform For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs, and begins to float when a 100 mV ...
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... SCA0 SCL0 (NC) XTAL2 CLOCK SDA1 XTAL1 SIGNAL SCL1 V SS All other pins disconnected 1323 F59 P1.4 P1.5 P0 P1.6 P1.7 EA# RST XTAL2 (NC) XTAL1 V SS All other pins disconnected 1323 F60.0 72 FlashFlex MCU SST89C58RC Max Units µs 100 µs T12-9.0 1323 S71323-02-000 02/08 ...
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... Voltage Range C = 2.7-5.5V Product Series 89 = C51 Core 1. Environmental suffix “E” denotes non-Pb solder. SST non-Pb solder devices are “RoHS Compliant”. 2. Environmental suffix “F” denotes non-Pb/non-SN solder. SST non-Pb/non-Sn solder devices are “RoHS Compliant”. SST89C58RC-40-I-QIF 73 Preliminary Specification S71323-02-000 02/08 ...
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... Silicon Storage Technology, Inc. SIDE VIEW .147 .020 R. .158 MAX. .025 .042 R. x45° .045 .056 .013 .021 .500 .590 .026 .032 REF. .630 .050 BSC. .020 Min. .100 .112 .165 .180 74 FlashFlex MCU SST89C58RC BOTTOM VIEW .026 .032 44-plcc-NJ-7 S71323-02-000 02/08 ...
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... FlashFlex MCU SST89C58RC Pin #1 Identifier 10.00 ± 0.10 12.00 ± 0.25 1.2 max. Note: 1. Complies with JEDEC publication 95 MS-026 ACB dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (±0.05) mm. 4. Package body dimensions do not include mold flash. Maximum allowable mold flash is .25mm. ...
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... FIGURE 14-3: 40-Contact Very-Very-Thin Quad Flat No-lead (WQFN) SST Package Code: QI ©2008 Silicon Storage Technology, Inc. SIDE VIEW 0.2 6.00 ± 0.10 0.075 0.05 Max 0.80 0. FlashFlex MCU SST89C58RC BOTTOM VIEW See notes 2 and 3 Pin #1 0.5 BSC 4.1 0.30 4.1 0.18 0.45 0.35 1mm leads ...
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... FlashFlex MCU SST89C58RC TABLE 14-1: Revision History Number 00 • Initial Release of data sheet 01 • Added QIF non-pb (F) ordering info • Edited Product Description • Fixed typo in Figure 2-1, edited Table 2-1 • Text changes on page 11 and text changes to Figure 3-1 • ...