AT90USB646-16MU Atmel, AT90USB646-16MU Datasheet - Page 14
![Microcontrollers (MCU) AVR USB 64K FLASH5V](/photos/39/69/396955/mlf_qfn-64_sml.jpg)
AT90USB646-16MU
Manufacturer Part Number
AT90USB646-16MU
Description
Microcontrollers (MCU) AVR USB 64K FLASH5V
Manufacturer
Atmel
Datasheet
1.AT90USB1287-16MU.pdf
(30 pages)
Specifications of AT90USB646-16MU
Data Bus Width
8 bit
Program Memory Type
Flash
Program Memory Size
64 KB
Data Ram Size
4 KB
Interface Type
2-Wire, SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
48
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
QFN-64
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / Rohs Status
Details
Other names
AT90USB646-MU
5. Instruction Set Summary
14
Mnemonics
FMULSU
MULSU
FMULS
EICALL
RCALL
MULS
EIJMP
ICALL
SBRC
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRGE
BRHS
BRHC
ADIW
FMUL
RJMP
CPSE
SBRS
BRBS
BRLO
BRPL
BRTS
BRTC
BRVS
SBIW
ANDI
CALL
BRMI
BRLT
SUBI
SBCI
COM
IJMP
RETI
SBIC
SBIS
ADD
ADC
SUB
SBC
AND
EOR
NEG
SBR
CBR
DEC
CLR
SER
MUL
JMP
RET
CPC
ORI
TST
INC
CPI
OR
CP
AT90USB64/128
Operands
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd, Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rdl,K
Rd, K
Rd, K
Rdl,K
Rd, K
Rd, K
Rd,K
Rd,K
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
Rd
Rd
Rd
Rd
Rd
Rd
Rd
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
Fractional Multiply Signed with Unsigned
Subtract with Carry Constant from Reg.
Logical AND Register and Constant
Branch if Greater or Equal, Signed
Logical OR Register and Constant
Compare Register with Immediate
Subtract with Carry two Registers
Branch if Less Than Zero, Signed
Skip if Bit in I/O Register Cleared
Branch if Half Carry Flag Cleared
Subtract Constant from Register
Subtract Immediate from Word
Skip if Bit in I/O Register is Set
Multiply Signed with Unsigned
Extended Indirect Jump to (Z)
Branch if Overflow Flag is Set
Skip if Bit in Register Cleared
Branch if Status Flag Cleared
Add with Carry two Registers
Fractional Multiply Unsigned
Branch if Half Carry Flag Set
Extended Indirect Call to (Z)
Skip if Bit in Register is Set
Fractional Multiply Signed
Branch if Same or Higher
Branch if Status Flag Set
Branch if T Flag Cleared
Relative Subroutine Call
Add Immediate to Word
Exclusive OR Registers
Branch if Carry Cleared
Compare, Skip if Equal
Subtract two Registers
Logical AND Registers
Clear Bit(s) in Register
Test for Zero or Minus
Direct Subroutine Call
Logical OR Registers
Set Bit(s) in Register
Compare with Carry
Branch if T Flag Set
One’s Complement
Two’s Complement
Indirect Jump to (Z)
Branch if Not Equal
Branch if Carry Set
Add two Registers
Subroutine Return
Indirect Call to (Z)
Multiply Unsigned
Interrupt Return
Branch if Lower
Multiply Signed
Branch if Equal
Branch if Minus
Description
Clear Register
Relative Jump
Branch if Plus
Set Register
Direct Jump
Decrement
Increment
Compare
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (Rd = Rr) PC ← PC + 2 or 3
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
R1:R0 ← (Rd x Rr)
R1:R0 ← (Rd x Rr)
R1:R0 ← (Rd x Rr)
Rdh:Rdl ← Rdh:Rdl + K
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • (0xFF - K)
Rd ← Rd + Rr + C
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
R1:R0 ← Rd x Rr
PC ← PC + k + 1
Rd ← Rd - Rr - C
PC ← PC + k + 1
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd - K - C
Rd ← Rd ⊕ Rd
PC ←(EIND:Z)
PC ←(EIND:Z)
Rd ← Rd ⊕ Rr
Rd ← Rd • Rd
Rd ← Rd + Rr
Rd ← Rd • Rr
Rd ← Rd v Rr
PC ← STACK
PC ← STACK
Rd ← Rd - Rr
Rd ← Rd • K
Rd ← Rd v K
Rd ← Rd v K
Rd ← Rd + 1
Rd ← Rd − 1
Operation
Rd ← Rd - K
Rd ← 0xFF
Rd − Rr − C
PC ← Z
PC ← Z
PC ← k
PC ← k
Rd − Rr
Rd − K
<< 1
<< 1
<< 1
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,S
Z,C,N,V
Flags
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Z,C
Z,C
Z,C
Z,C
Z,C
Z,C
I
7593GS–AVR–03/08
#Clocks
1/2/3
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
2
2
2
3
4
4
4
5
5
5
1
1
1