LMX3162VBH National Semiconductor, LMX3162VBH Datasheet - Page 12

• Manufacturer Part Number: LMX3162VBH
• Description: IC TXRX RADIO SNG CHIP 48-LQFP
• Manufacturer: National Semiconductor
• Type: Transceiverr

Specifications of LMX3162VBH

• Voltage - Supply: 3 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Drivers/receivers: -
• Protocol: -
• Other names: *LMX3162VBH

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MICROWIRE
t
t
t
t
t
t
CS
CH
CWH
CWL
ES
EW
Serial Data Input Timing
Symbol
PLL Functional Description
The simplified block diagram below shows the building blocks of frequency synthesizer and all internal registers, which are 20-bit
data register, 18-bit F-latch, 13-bit N-counter, and 5-bit R-counter.
The DATA stream is clocked into the data register on the rising edge of CLOCK signal, MSB first. The last two bits are the control
bits to indicate which register to be written. Upon the rising edge of the LE (Load Enable) signal, the rest of data bits is transferred
to the addressed register accordingly. The decoding scheme of the two control bits is as follows:
Programmable Feedback Divider (N-Counter)
The N-counter consists of the 6-bit swallow counter (A-counter) and the 7-bit programmable counter (B-counter). When the con-
trol bits are “00”, data is transferred from the 20-bit shift register into two latches. One latch sets the A-counter while the other sets
the B-counter. The serial data format is shown below.
Note: X = Don’t Care Condition
Swallow Counter Divide Ratio (A-Counter)
MSB
19
X
18
X
RESERVED
™
Data to Clock Set Up Time
Data to Clock Hold Time
Clock Pulse Width High
Clock Pulse Width Low
Clock to Load Enable Set Up Time
Load Enable Pulse Width
Interface
17
X
16
X
Parameter
Note: X = Don’t Care Condition
15
Divide Ratio, A
X
N13
C2
14
X
63
0
1
0
1
*
Control Bits
(Continued)
N12
13
N11
12
N6
0
0
1
*
REGISTER’S BIT MAPPING
C1
N10
Refer to Test Condition.
Refer to Test Condition.
Refer to Test Condition.
Refer to Test Condition.
Refer to Test Condition.
Refer to Test Condition.
0
0
1
11
N5
0
0
1
*
N-COUNTER’s Divide Ratio
12
N9
10
Conditions
N4
N-Counter
R-Counter
F-Latch
0
0
*
1
N8
9
N3
N7
0
0
1
*
8
Register
N6
N2
7
0
0
*
1
Min
50
10
50
50
50
50
N5
6
N1
0
1
1
*
N4 N3 N2 N1
5
Typ
—
—
—
—
—
—
DS100929-4
4
3
Max
—
—
—
—
—
—
2
C2 C1
1
0
Unit
LSB
ns
ns
ns
ns
ns
ns
0
0