SAF7118EH/V1/G,557 Trident Microsystems, Inc., SAF7118EH/V1/G,557 Datasheet - Page 123

• Manufacturer Part Number: SAF7118EH/V1/G,557
• Manufacturer: Trident Microsystems, Inc.

Specifications of SAF7118EH/V1/G,557

• Lead Free Status / Rohs Status: Supplier Unconfirmed

NXP Semiconductors
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
SAF7118_4
Product data sheet
Subaddress
30h
31h
32h
Subaddress
34h
35h
36h
Subaddress
38h
Subaddress
39h
Bit
D3
D2
D1
D0
Audio master clock (AMCLK) cycles per field
Audio master clock (AMCLK) nominal increment
Clock ratio audio master clock (AMXCLK) to serial bit clock (ASCLK)
Clock ratio serial bit clock (ASCLK) to channel select clock (ALRCLK)
Audio clock control; 3Ah[3:0]
Description
audio PLL modes
audio master clock vertical
reference
ALRCLK phase
ASCLK phase
10.5.1 Subaddresses 30h to 32h
10.5.2 Subaddresses 34h to 36h
10.5.3 Subaddress 38h
10.5.4 Subaddress 39h
10.5.5 Subaddress 3Ah
10.5 Programming register audio clock generation
Control bits D7 to D0
ACPF7
ACPF15
-
Control bits D7 to D0
ACNI7
ACNI15
-
Control bits D7 to D0
-
Control bits D7 to D0
-
See equations in
ACPF6
ACPF14
-
ACNI6
ACNI14
-
-
-
Section 8.7
Symbol
APLL
AMVR
LRPH
SCPH
ACPF5
ACPF13
-
ACNI5
ACNI13
ACNI21
SDIV5
LRDIV5
Rev. 04 — 4 July 2008
and examples in
ACPF4
ACPF12
-
ACNI4
ACNI12
ACNI20
SDIV4
LRDIV4
Multistandard video decoder with adaptive comb filter
Value
0
1
0
1
0
1
0
1
ACPF3
ACPF11
-
ACNI3
ACNI11
ACNI19
SDIV3
LRDIV3
Function
PLL active, AMCLK is field-locked
PLL open, AMCLK is free-running
vertical reference pulse is taken from internal
decoder
vertical reference is taken from XRV input
(expansion port)
ALRCLK edges triggered by falling edges of
ASCLK
ALRCLK edges triggered by rising edges of
ASCLK
ASCLK edges triggered by falling edges of
AMCLK
ASCLK edges triggered by rising edges of AMCLK
Table 22
ACPF2
ACPF10
-
ACNI2
ACNI10
ACNI18
SDIV2
LRDIV2
and
Table
23.
ACPF1
ACPF9
ACPF17
ACNI1
ACNI9
ACNI17
SDIV1
LRDIV1
SAF7118
© NXP B.V. 2008. All rights reserved.
ACPF0
ACPF8
ACPF16
ACNI0
ACNI8
ACNI16
SDIV0
LRDIV0
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