DS26324GN+ Maxim Integrated Products, DS26324GN+ Datasheet - Page 58

• Manufacturer Part Number: DS26324GN+
• Description: IC LIU 16CH T1/E1/J1 256CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Line Interface Units (LIUs)r

Specifications of DS26324GN+

• Number Of Drivers/receivers: 16/16
• Protocol: LIN
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register Name:
Register Description:
Register Address (LIUs 1–8):
Bit #
Name
Default
Bits 7 and 6: Jitter Attenuator Bandwidth Selection [1:0] (JABWS[1:0]). In E1 mode, JABWS[1:0] is used to
control the bandwidth of the jitter attenuator according to the following table:
Bit 5: Receive Hitless Protection Mode Control (RHPMC). When this bit is set, the receive impedance match
on/off selection will be controlled by the OE pin. If OE is high, receive impedance match is on. If OE is low, receive
impedance match is off (Internal impedance to RTIP and RRING is high impedance). When this bit is reset, the
RIMPON register bit will control receive impedance match.
Bits 2 to 0: TST Template Select Transceiver [2:0] (TST[2:0]). TST[2:0] is used to select the transceiver that the
Transmit Template Select Register (0x11) will configure for LIUs 1–8. See
Register Address (LIUs 9–16):
Bit #
Name
Default
Bits 7 and 6: Jitter Attenuator Bandwidth Selection [1:0] (JABWS[1:0]). In E1 mode, JABWS[1:0] is used to
control the bandwidth of the jitter attenuator according to the following table:
Bit 5: Receive Hitless Protection Mode Control (RHPMC). When this bit is set, the receive impedance match
on/off selection will be controlled by the OE pin. If OE is high, receive impedance match is on. If OE is low, receive
impedance match is off (internal impedance to RTIP and RRING is high impedance). When this bit is reset, the
RIMPON register bit will control receive impedance match.
Bits 2 to 0: TST Template Select Transceiver [2:0] (TST[2:0]). TST[2:0] is used to select the transceiver that the
Transmit Template Select Register (0x11) will configure for LIUs 9–16. See
JABWS
JABWS
00
01
10
11
00
01
10
11
JABWS1
JABWS1
7
0
7
0
BANDWIDTH (Hz)
BANDWIDTH (Hz)
JABWS0
JABWS0
6
0
6
0
0.625
0.625
1.25
1.25
2.5
2.5
5
5
TST
Template Select Transmitter
10h
30h
RHPMC
RHPMC
5
0
5
0
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
58 of 120
—
—
4
0
4
0
—
—
3
0
3
0
Table
Table
TST2
TST2
6-11.
2
0
2
0
6-12.
TST1
TST1
1
0
1
0
TST0
TST0
0
0
0
0