DS26324G+ Maxim Integrated Products, DS26324G+ Datasheet - Page 85
![IC LIU 16CH T1/E1/J1 256CSBGA](/photos/6/50/65053/256-csbga_21-0315_sml.jpg)
DS26324G+
Manufacturer Part Number
DS26324G+
Description
IC LIU 16CH T1/E1/J1 256CSBGA
Manufacturer
Maxim Integrated Products
Type
Line Interface Units (LIUs)r
Datasheet
1.DS26324GNTR.pdf
(120 pages)
Specifications of DS26324G+
Number Of Drivers/receivers
16/16
Protocol
LIN
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 85 of 120
- Download datasheet (2Mb)
Register Name:
Register Description:
Register Address (LIUs 1–8):
Register Address (LIUs 9–16):
Bit #
Name
Default
Bit 6: QRSS Enable (QRSS). When 0, the pattern generator configuration is controlled by PTS, PLF[4:0], and
PTF[4:0], and BSP[31:0]. When 1, the pattern generator configuration is forced to a PRBS pattern with a
generating polynomial of x
output bits are all zero.
Bit 5: Pattern Type Select (PTS). When 0, the pattern is a PRBS pattern. When 1, the pattern is a repetitive
pattern.
Bits 4 to 0: Pattern Length Feedback (PLF[4:0]). These five bits control the “length” feedback of the pattern
generator. The “length” feedback will be from bit n of the pattern generator (n = PLF[4:0] +1). For a PRBS signal,
the feedback is an XOR of bit n and bit y. For a repetitive pattern the feedback is bit n.
Register Name:
Register Description:
Register Address (LIUs 1–8):
Register Address (LIUs 9–16):
Bit #
Name
Default
Bits 4 to 0: Pattern Tap Feedback (PTF[4:0]). These five bits control the PRBS “tap” feedback of the pattern
generator. The “tap” feedback will be from bit y of the pattern generator (y = PTF[4:0] +1). These bits are ignored
when programmed for a repetitive pattern. For a PRBS signal, the feedback is an XOR of bit n and bit y.
—
—
7
0
7
0
QRSS
20
—
+ x
6
0
6
0
17
BPCR1
BERT Pattern Configuration Register 1
02h
22h
BPCR2
BERT Pattern Configuration Register 2
03h
23h
+ 1. The output of the pattern generator will be forced to one if the next fourteen
PTS
—
5
0
5
0
DS26324 3.3V, 16-Channel, E1/T1/J1 Short-Haul Line Interface Unit
PTF4
85 of 120
PLF4
4
0
4
0
PLF3
PTF3
3
0
3
0
PLF2
PTF2
2
0
2
0
PLF1
PTF1
1
0
1
0
PLF0
PTF0
0
0
0
0
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