DS26528G+ Maxim Integrated Products, DS26528G+ Datasheet - Page 168
DS26528G+
Manufacturer Part Number
DS26528G+
Description
IC TXRX T1/E1/J1 OCT 256-CSBGA
Manufacturer
Maxim Integrated Products
Type
Transceiverr
Datasheet
1.DS26528G.pdf
(276 pages)
Specifications of DS26528G+
Number Of Drivers/receivers
4/4
Protocol
IEEE 1149.1
Voltage - Supply
3.135 V ~ 3.465 V
Mounting Type
Surface Mount
Package / Case
256-CSBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Note: For E1 mode, see RIM3.
Bit 7: Loss of Receive Clock Condition Clear (LORCC).
Bit 6: Spare Code Detected Condition Clear (LSPC).
Bit 5: Loop-Down Code Detected Condition Clear (LDNC).
Bit 4: Loop-Up Code Detected Condition Clear (LUPC).
Bit 3: Loss of Receive Clock Condition Detect (LORCD).
Bit 2: Spare Code Detected Condition Detect (LSPD).
Bit 1: Loop-Down Code Detected Condition Detect (LDND).
Bit 0: Loop-Up Code Detected Condition Detect (LUPD).
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
0 = interrupt masked
1 = interrupt enabled
LORCC
7
0
RIM3 (T1 Mode)
Receive Interrupt Mask Register 3
0A2h + (200h x n): where n = 0 to 7, for Ports 1 to 8
LSPC
6
0
LDNC
5
0
168 of 276
LUPC
4
0
LORCD
3
0
DS26528 Octal T1/E1/J1 Transceiver
LSPD
2
0
LDND
1
0
LUPD
0
0
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