DS21Q59LN+ Maxim Integrated Products, DS21Q59LN+ Datasheet - Page 54

• Manufacturer Part Number: DS21Q59LN+
• Description: IC TXRX E1 QUAD 100-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS21Q59LN+

• Number Of Drivers/receivers: 4/4
• Protocol: E1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Dc: 1136
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

23.
In many architectures, the PCM outputs of individual framers are combined into higher-speed PCM buses to
simplify transport across the system backplane. The DS21Q59 can be configured to allow PCM data buses to be
multiplexed into higher-speed data buses, eliminating external hardware and saving board space and cost. The
DS21Q59 uses a channel interleave method. See
The interleaved PCM bus option supports three bus speeds. The 4.096MHz bus speed allows two PCM data
streams to share a common bus. The 8.192MHz bus speed allows four PCM data streams to share a common bus.
The 16.384MHz bus speed allows eight PCM data streams to share a common bus. See
example of four transceivers sharing a common 8.192MHz PCM bus. The receive elastic stores of each transceiver
must be enabled. Through the IBO register the user can configure each transceiver for a specific bus speed and
position. For all IBO bus configurations each transceiver is assigned an exclusive position in the high-speed PCM
bus. When the device is configured for IBO operation, the TSYNCx pin should be configured as an output or as an
input connected to ground. The user cannot supply a TSYNCx signal in this mode. When IBO operation is enabled,
TSYNCx will be internally tied to RSYNCx. If TSYNCx is configured as an input, the physical pin will be
disconnected from the internal TSYNCx signal and should therefore be connected to ground to keep it from
floating.
Register Name:
Register Description:
Register Address:
Bit #
Name
Table 23-A. IBO System Clock Select
SCS1
IBOTCS
IBOEN
NAME
SCS1
SCS0
0
0
1
1
DA2
DA1
DA0
—
INTERLEAVED PCM BUS OPERATION
SCS0
0
1
0
1
—
7
BIT
2.048MHz, single device on bus
4.096MHz, two devices on bus
8.192MHz, four devices on bus
16.384MHz, eight devices on bus
7
6
5
4
3
2
1
0
IBOTCS
6
Not Assigned. Should be set to 0.
IBO Transmit Clock Source
0 = TCLK pin is the source of transmit clock
1 = Transmit clock is internally derived from the clock at the SYSCLK pin
System Clock Select Bit 1
System Clock Select Bit 0
Interleave Bus Operation Enable
0 = IBO disabled
1 = IBO enabled
Device Assignment Bit 3
Device Assignment Bit 2
Device Assignment Bit
FUNCTION
IBO
Interleave Bus Operation Register
1C Hex
SCS1
5
SCS0
Figure 24-4
4
1(Table
54 of 76
(Table
(Table
(Table
(Table
Table 23-B. IBO Device Assignment
23-B)
23-B)
23-B)
IBOEN
FUNCTION
23-A)
23-A)
DA2
and
0
0
0
0
1
1
1
1
3
Figure 24-7
DA1
0
0
1
1
0
0
1
1
DA2
2
DA0
for details of the channel interleave.
0
1
0
1
0
1
0
1
DA1
1
2nd device on bus
1st device on bus
3rd device on bus
4th device on bus
5th device on bus
6th device on bus
7th device on bus
8th device on bus
FUNCTION
Figure 23-1
DA0
0
for an