DS2154LN+ Maxim Integrated Products, DS2154LN+ Datasheet - Page 55

• Manufacturer Part Number: DS2154LN+
• Description: IC TXRX E1 1CHIP 5V ENH 100-LQFP
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS2154LN+

• Number Of Drivers/receivers: 1/1
• Protocol: E1
• Voltage - Supply: 4.75 V ~ 5.25 V
• Mounting Type: Surface Mount
• Package / Case: 100-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

10 CLOCK BLOCKING REGISTERS
The Receive Channel Blocking Registers (RCBR1/RCBR2/RCBR3/RCBR4) and the Transmit Channel
Blocking Registers (TCBR1/TCBR2/TCBR3/TCBR4) control the RCHBLK and TCHBLK pins,
respectively. The RCHBLK and TCHCLK pins are user-programmable outputs that can be forced either
high or low during individual channels. These outputs can be used to block clocks to a USART or LAPD
controller in ISDN-PRI applications. When the appropriate bits are set to 1, the RCHBLK and TCHCLK
pins will be held high during the entire corresponding channel time. See the timing diagrams in Section
14
use the TCBRs to determine, on a channel-by-channel basis, which signaling bits are to be inserted via
the TSRs (the corresponding bit in the TCBRs = 1) and which are to be sourced from the TSER or TSIG
pins (the corresponding bit in the TCBR = 0). See Section
operation.
RCBR1/RCBR2/RCBR3/RCBR4: RECEIVE CHANNEL BLOCKING
REGISTERS (Address = 2B to 2E Hex)
TCBR1/TCBR2/TCBR3/TCBR4: TRANSMIT CHANNEL BLOCKING
REGISTERS (Address = 22 to 25 Hex)
(MSB)
(MSB)
CH16
CH24
CH32
CH16
CH24
CH32
for an example. The TCBRs have alternate mode of use. Via the CCR3.6 bit, the user has the option to
CH8
CH8
SYMBOL
CH32
CH1
SYMBOL
CH32
CH1
CH15
CH23
CH31
CH15
CH23
CH31
CH7
CH7
POSITION
RCBR4.7
RCBR1.0
POSITION
CH14
CH22
CH30
CH14
CH22
CH30
TCBR4.7
TCBR1.0
CH6
CH6
CH13
CH21
CH29
CH13
CH21
CH29
CH5
CH5
NAME AND DESCRIPTION
NAME AND DESCRIPTION
Receive Channel Blocking Registers.
0 = force the RCHBLK pin to remain low during this channel
time
1 = force the RCHBLK pin high during this channel time
Transmit Channel Blocking Registers.
0 = force the TCHBLK pin to remain low during this channel
time
1 = force the TCHBLK pin high during this channel time
CH12
CH20
CH28
CH12
CH20
CH28
CH4
CH4
55 of 87
CH11
CH19
CH27
CH11
CH19
CH27
CH3
CH3
8
for more details about this mode of
CH10
CH18
CH26
CH10
CH18
CH26
CH2
CH2
(LSB)
CH17
CH25
CH17
CH25
CH1
CH9
CH1
CH9
(LSB)
RCBR1 (2B)
RCBR2 (2C)
RCBR3 (2D)
RCBR4 (2E)
TCBR1 (22)
TCBR1 (23)
TCBR1 (24)
TCBR4 (25)