MCIMX537CVV8C Freescale Semiconductor, MCIMX537CVV8C Datasheet - Page 49

• Manufacturer Part Number: MCIMX537CVV8C
• Description: IC, 32-BIT MPU, 800 MHz, 529-BGA
• Manufacturer: Freescale Semiconductor
• Series: ARM Cortex-A8r

Specifications of MCIMX537CVV8C

• Core Size: 32bit
• Program Memory Size: 288KB
• Cpu Speed: 1GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 529
• Operating Temperature Range: -20°C To +85°C
• Msl: MSL 3 - 168 Hours
• Lead Free Status / Rohs Status: Supplier Unconfirmed

Freescale Semiconductor
1
2
3
t
Asymmetric mode:
Symmetric mode:
t
where t
EXTMC including I/O pad delay.
t
Tdl is composed of 4 delay-line units each generates an equal delay with min 1.25 ns and max 1 aclk period (T
is 1/4 aclk period for each delay-line unit, so all 4 delay lines together generates a total of 1 aclk period. T
“emi_slow_clk” of the system, which default value is 7.5 ns (133 MHz).
NF17 is defined only in asymmetric operation mode.
NF17 max value is equivalent to max t
T
NF16
NF17
NF18
NF10
NF11
NF12
NF13
NF14
NF15
NF19
NF20
NF21
NF22
DSR
REpd
DSR
aclk
NF1
NF2
NF3
NF4
NF5
NF6
NF7
NF8
NF9
ID
is calculated by the following formula:
is “emi_slow_clk” of the system.
can be used to determine t
1
3
4
+ t
REpd
Dpd
NFRE_B High Hold Time
= 11.2 ns (including clock skew)
is RE propogation delay in the chip including I/O pad delay, and t
Ready to NFRE_B Low
NFWE_B Pulse Width
NFRE_B Pulse Width
Data Setup on READ
NFCE_B Setup Time
NFWE_B Hold Time
Data Hold on READ
Data Hold on READ
NFCE_B Hold Time
NFCLE setup Time
NFALE Setup Time
WE high to RE low
NFCLE Hold Time
NFALE Hold Time
READ Cycle Time
Write Cycle Time
Data Setup Time
CLE to RE delay
WE high to busy
Data Hold Time
CE to RE delay
Parameter
t
t
DSR =
DSR =
i.MX53xD Applications Processors for Consumer Products, Rev. 1
t
t
REpd
REpd
REA
+ t
+ t
Dpd +
max parameter with the following formula: t
Table 34. NFC—Timing Characteristics
Dpd
RHZ
– Tdl
1
/
2
value that can be used with NFC.
T – Tdl
Symbol
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
WHR
t
t
t
t
t
t
t
t
REH
DSR
DHR
DHR
CRE
CLS
CLH
ALH
CLR
ALS
WP
WC
WH
WB
CS
CH
DS
DH
RR
RP
RC
2
Asymmetric Mode Min
11.2 + 0.5T – Tdl
0.5T – 1.15
14T – 5.45
3T + 0.95
3T – 5.55
13T + 1.5
2T + 0.1
2T + 0.1
9T + 8.9
T – 4.45
T – 4.45
T – 5.55
T – 1.15
T – 3.45
T – 1.4
T – 0.9
1.5T
2T
2T
—
—
0
Dpd
2
REA =
is Data propogation delay from I/O pad to
Symmetric Mode
1.5T – t
0.5T – 5.55
0.5T – 1.15
0.5T – 1.15
11.2 – Tdl
Tdl
14T – 5.45
0.5T – 1.4
0.5T – 0.9
13T + 1.5
3T – 5.55
2T + 0.1
T – 4.45
3T+0.95
2T + 0.1
T – 4.45
9T + 8.9
T – 3.45
0.5T
2
Min
—
—
DSR
T
T
– 11.2
Electrical Characteristics
.
2
aclk
is
2T
2T
aclk
T + 0.3
aclk
aclk
Max
6T
). Default
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
+ T
+ T
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