ATA6602-EK Atmel, ATA6602-EK Datasheet - Page 188

• Manufacturer Part Number: ATA6602-EK
• Manufacturer: Atmel

Specifications of ATA6602-EK

• Lead Free Status / Rohs Status: Supplier Unconfirmed

188
ATA6602/ATA6603
Table 4-67.
Table 4-68.
Table 4-69.
• Bit 4 – MSTR: Master/Slave Select
• Bit 3 – CPOL: Clock Polarity
• Bit 2 – CPHA: Clock Phase
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
This bit selects Master SPI mode when written to one, and Slave SPI mode when written
logic zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to
re-enable SPI Master mode.
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is
low when idle. Refer to
is summarized below:
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to
The CPOL functionality is summarized below:
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0
have no effect on the Slave. The relationship between SCK and the Oscillator Clock fre-
quency f
SPI2X
0
0
0
0
1
1
1
1
CPOL
CPHA
osc
CPOL Functionality
CPHA Functionality
Relationship Between SCK and the Oscillator Frequency
0
1
0
1
is shown in the following table:
SPR1
Figure 4-67
0
0
1
1
0
0
1
1
Leading Edge
Leading Edge
and
Sample
Falling
Rising
Setup
Figure 4-68
SPR0
0
1
0
1
0
1
0
1
Figure 4-67
for an example. The CPOL functionality
SCK Frequency
f
f
f
f
f
f
f
f
osc
osc
osc
osc
osc
osc
osc
osc
/
/
/
/
/
/
/
/
4
16
64
128
2
8
32
64
and
Figure 4-68
Trailing Edge
Trailing Edge
Sample
Falling
Rising
Setup
for an example.
4921E–AUTO–09/09