ADL5565AXPZ-R7 Analog Devices Inc, ADL5565AXPZ-R7 Datasheet - Page 16

• Manufacturer Part Number: ADL5565AXPZ-R7
• Manufacturer: Analog Devices Inc

Specifications of ADL5565AXPZ-R7

• Lead Free Status / Rohs Status: Compliant

ADL5565
Table 5. Evaluation Board Configuration Options
Component
VPOS, GND
C3, C4, C5,
C6, C7, C11
J1, J2, R1, R2,
R3, R4, R5, R6,
R12, R13,
C1, C2, C12,
T1
J3, J4, R7, R8,
R9, R10, R11,
R14, R15
C9, C10, C13,
T2
ENBL, P1, C8
Table 6. Differential Values for Figure 11
GAIN (dB)
6
12
15.5
Table 7.
GAIN (dB)
6
12
15.5
Alternative Differential Input Configuration Figure 11
Description
Ground and supply vector pins.
Power supply decoupling. The supply decoupling consists of a 10 μF capacitor (C3)
to ground. C4 to C7 are bypass capacitors. C11 ac couples VREF to ground.
Input interface. The SMA labeled J1 is the input. T1 is a 1-to-1 impedance ratio balun
to transform a single-ended input into a balanced differential signal. Removing R13
installing R12, 0 Ω and installing SMA connector, J2, allows driving from a differential
source. C1 and C2
provide ac coupling. C12 is a bypass capacitor. R1 and R2 provide a differential 50 Ω
input termination. R3 to R6 are used to select the input for the pin-strappable gain.
Maximum gain: R3, R4, R5, R6 = 0 Ω; and R1, R2 = open. Middle gain: R5, R6 = 0 Ω; and R3,
R4 = open; R1, R2 = 50 Ω. Minimum gain: R3, R4 = 0 Ω; and R5, R6 = open; R1, R2 = 33.2 Ω.
Output interface. The SMA labeled J3 is the output. T2 is a 1-to-1 impedance ratio
balun to transform a balanced differential signal to a single-ended signal. Removing R14
and installing R15, 0 Ω, and SMA connector, J4, allows differential loading.
C13 is a bypass capacitor. R7, R8, R9, and R10 are provided for generic placement of
matching components.
The evaluation board is configured to provide a 200 Ω to 50 Ω impedance
transformation with an insertion loss of 17 dB. C9 and C10 provide ac coupling.
Device enable. C8 is a bypass capacitor. When the P1 jumper is set toward the VPOS label,
the ENBL pin is connected to the supply, enabling the device. In the opposite direction,
toward the GND label, the ENBL pin is grounded, putting the device in power-down mode.
R1 & R2 (Ω)
open
open
open
C12 (μF)
0.1
0.1
0.1
Rev. PrB | Page 16 of 18
R1 (Ω)
33.2
50
open
C1 & C2
0 Ω
0 Ω
0 Ω
Preliminary Technical Data
T1
Mini Circuits TC4-1W+
Mini Circuits TC2-1T+
Mini Circuits TC1.5-52T+
Default Condition
VPOS, GND = installed
C3 = 10 μF (Size D),
C4, C5, C6, C7, C11 = 0.1 μF (Size 0402)
J1 = installed,
J2 = not installed,
R1, R2 = open,
R3, R4, R5, R6, R13 = 0 Ω (Size 0402),
R12, = open,
C1, C2 = 0.01 μF (Size 0402),
C12 = open,
T1 = ETC1-1-13 (M/A-COM)
J3 = installed,
J4 = not installed,
R7, R8 = 84.5 Ω (Size 0402),
R9, R10 = 34.8 Ω (Size 0402),
R11, R15 = open (Size 0402),
R15 = 0 Ω (Size 0402)
C9, C10 = 0.01 μF (Size 0402),
C13 = open
T2 = ETC1-1-13 (M/A-COM)
ENBL, P1= installed,
C8 = 0.1 μF (Size 0402)
R2 (Ω)
33.2
50
open