MK60DX256ZVLQ10 Freescale Semiconductor, MK60DX256ZVLQ10 Datasheet - Page 39

• Manufacturer Part Number: MK60DX256ZVLQ10
• Description: KINETIS 256KFLEX ENET
• Manufacturer: Freescale Semiconductor

Specifications of MK60DX256ZVLQ10

• Processor Series: K60
• Core: ARM Cortex M4
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 128 KB
• Interface Type: USB, CAN, SPI, I2C, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 2
• Number Of Timers: 2
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-144
• Operating Temperature Range: - 40 C to + 105 C
• Processor To Be Evaluated: MK60DX256ZVLQ10
• Supply Current (max): 185 mA

6.4.2 EzPort Switching Specifications
6.4.3 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
Freescale Semiconductor, Inc.
EZP_CK
EZP_CS
EZP_Q (output)
EZP_D (input)
EP1a
Num
EP1
EP2
EP3
EP4
EP5
EP6
EP7
EP8
EP9
Operating voltage
EZP_CK frequency of operation (all commands except
READ)
EZP_CK frequency of operation (READ command)
EZP_CS negation to next EZP_CS assertion
EZP_CS input valid to EZP_CK high (setup)
EZP_CK high to EZP_CS input invalid (hold)
EZP_D input valid to EZP_CK high (setup)
EZP_CK high to EZP_D input invalid (hold)
EZP_CK low to EZP_Q output valid (setup)
EZP_CK low to EZP_Q output invalid (hold)
EZP_CS negation to EZP_Q tri-state
Description
K60 Sub-Family Data Sheet Data Sheet, Rev. 5, 5/2011.
Table 24. EzPort switching specifications
EP3
Figure 10. EzPort Timing Diagram
EP5
EP6
EP4
EP7
Preliminary
EP8
EP9
Peripheral operating requirements and behaviors
EP2
2 x t
1.71
Min.
—
—
EZP_CK
—
—
5
5
2
5
0
f
f
Max.
SYS
SYS
3.6
12
12
—
—
—
—
—
—
/2
/8
MHz
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
V
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