MK60DX256ZVLL10 Freescale Semiconductor, MK60DX256ZVLL10 Datasheet - Page 49

• Manufacturer Part Number: MK60DX256ZVLL10
• Description: KINETIS 256KFLEX ENET
• Manufacturer: Freescale Semiconductor

Specifications of MK60DX256ZVLL10

• Processor Series: K60
• Core: ARM Cortex M4
• Data Bus Width: 16 bit
• Program Memory Type: Flash
• Program Memory Size: 256 KB
• Data Ram Size: 128 KB
• Interface Type: USB, CAN, SPI, I2C, UART
• Maximum Clock Frequency: 100 MHz
• Number Of Programmable I/os: 2
• Number Of Timers: 2
• Operating Supply Voltage: 1.71 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: LQFP-100
• Operating Temperature Range: - 40 C to + 105 C
• Processor To Be Evaluated: MK60DX256ZVLL10
• Supply Current (max): 185 mA
• Lead Free Status / Rohs Status: Details

1. Typical values assume V
2. This current is a PGA module adder, in addition to and ADC conversion currents.
3. Between IN+ and IN-. The PGA draws a DC current from the input terminals. The magnitude of the DC current is a strong
4. Gain = 2
5. After changing the PGA gain setting, a minimum of 2 ADC+PGA conversions should be ignored.
6. Limit the input signal swing so that the PGA does not saturate during operation. Input signal swing is dependent on the
6.6.2 CMP and 6-bit DAC electrical specifications
Freescale Semiconductor, Inc.
Symbol
SINAD
Symbol
ENOB
SFDR
function of input common mode voltage (V
PGA reference voltage and gain setting.
SNR
THD
I
V
DDHS
DD
PGAG
Signal-to-noise
ratio
Total harmonic
distortion
Spurious free
dynamic range
Effective number
of bits
Signal-to-noise
plus distortion
ratio
Description
Supply voltage
Supply current, High-speed mode (EN=1, PMODE=1)
Description
Table 31. Comparator and 6-bit DAC electrical specifications
Table 30. 16-bit ADC with PGA characteristics (continued)
DDA
K60 Sub-Family Data Sheet Data Sheet, Rev. 6, 9/2011.
=3.0V, Temp=25°C, f
See ENOB
Conditions
• Gain=1
• Gain=64
• Gain=1
• Gain=64
• Gain=1
• Gain=64
• Gain=1, Average=4
• Gain=64, Average=4
• Gain=1, Average=32
• Gain=2, Average=32
• Gain=4, Average=32
• Gain=8, Average=32
• Gain=16, Average=32
• Gain=32, Average=32
• Gain=64, Average=32
Table continues on the next page...
CM
) and the PGA gain.
ADCK
=6MHz unless otherwise stated.
11.6
12.8
11.0
Min.
7.2
7.9
7.3
6.8
6.8
7.5
80
52
85
49
85
53
6.02 × ENOB + 1.76
Peripheral operating requirements and behaviors
1.71
Min.
—
Typ.
13.4
14.5
14.3
13.8
13.1
12.5
11.5
10.6
100
105
9.6
90
66
95
88
1
Typ.
—
—
Max.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Unit
bits
bits
bits
bits
bits
bits
bits
bits
bits
dB
dB
dB
dB
dB
dB
dB
Max.
200
3.6
mode,f
Average=32,
Average=32,
Average=32
differential
differential
differential
differential
f
f
in
in
mode,
mode,
mode,
Notes
=100Hz
=100Hz
16-bit
16-bit
16-bit
16-bit
in
z
Unit
μA
=100H
V
49