PIC32MX440F512H-80V/PT Microchip Technology, PIC32MX440F512H-80V/PT Datasheet - Page 64
PIC32MX440F512H-80V/PT
Manufacturer Part Number
PIC32MX440F512H-80V/PT
Description
512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 64 TQFP 10x10x1mm TRAY
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheet
1.TDGL001.pdf
(214 pages)
Specifications of PIC32MX440F512H-80V/PT
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
64-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX440F512H-80V/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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TABLE 4-14:
TABLE 4-15:
Legend:
Note
Legend:
Note
3000 DMACON
3010
3020 DMAADDR
3030 DCRCCON
3040 DCRCDATA
3050 DCRCXOR
1:
1:
DMASTAT
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See
information.
(1)
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
DMA GLOBAL REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY
DMA CRC REGISTERS MAP FOR PIC32MX340FXXXX/360FXXXX/440FXXXX/460XXXX DEVICES ONLY
31/15
31/15
ON
—
—
—
—
—
—
—
30/14
30/14
—
—
—
—
—
—
—
—
29/13
29/13
SIDL
—
—
—
—
—
—
—
SUSPEND
28/12
28/12
—
—
—
—
—
—
—
27/11
27/11
—
—
—
—
—
—
—
26/10
26/10
—
—
—
—
—
—
—
PLEN<3:0>
25/9
25/9
—
—
—
—
—
—
—
DCRCDATA<15:0>
DMAADDR<31:0>
DCRCXOR<15:0>
24/8
24/8
—
—
—
—
—
—
—
Bits
Bits
CRCEN
23/7
23/7
—
—
—
—
—
—
—
CRCAPP
22/6
22/6
—
—
—
—
—
—
—
Section 12.1.1 “CLR, SET and INV Registers”
21/5
21/5
—
—
—
—
—
—
—
—
20/4
20/4
Section 12.1.1 “CLR, SET and INV Registers”
—
—
—
—
—
—
—
—
RDWR
19/3
19/3
—
—
—
—
—
—
—
18/2
18/2
—
—
—
—
—
—
—
—
(1)
for more information.
17/1
17/1
—
—
—
DMACH<1:0>
—
—
—
CRCCH<1:0>
16/0
16/0
for more
—
—
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
0000
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