MCP79510-I/MS Microchip Technology, MCP79510-I/MS Datasheet - Page 9

• Manufacturer Part Number: MCP79510-I/MS
• Description: SPI GP RTCC, 1Kb EE, 64B SRAM, ID 10 MSOP 3x3mm TUBE
• Manufacturer: Microchip Technology

by issuing the EEWREN instruction
done by setting CS low and then clocking out the
proper instruction into the MCP795XX. After all eight
bits of the instruction are transmitted, CS must be
driven high to set the write enable latch. If the write
operation is initiated immediately after the EEWREN
instruction without CS driven high, data will not be writ-
ten to the array since the write enable latch was not
properly set.
After setting the write enable latch, the user may pro-
ceed by driving CS low, issuing either an EEWRITE,
IDWRITE or a SWRITE instruction, followed by the
remainder of the address, and then the data to be writ-
ten. Up to 8 bytes of data can be sent to the device
before a write cycle is necessary. The only restriction is
that all of the bytes must reside in the same page. Addi-
tionally, a page address begins with XXXX 0000 and
ends with XXXX X111. If the internal address counter
reaches XXXX X111 and clock signals continue to be
FIGURE 3-2:
FIGURE 3-3:
 2012 Microchip Technology Inc.
CS
SO
SCK
SCK
SCK
SI
CS
CS
SI
SI
0
0
0
0
24
7
1
0
1
0
25
0
6
2
0
2
Instruction
Instruction
BYTE EEWRITE SEQUENCE
PAGE EEWRITE SEQUENCE
5
26 27 28 29 30 31
3
0
Data Byte 2
3
0
0
4
4
0
4
3
5
0
5
0
(Figure
1
2
6
6
1
0
1
7
0
7
A
3-4). This is
0
8
7
A
8
7
A
32
7
9 10 11
A
6
9 10 11
6
Address Byte
High-Impedance
A
33 34 35
6
Preliminary
A
5
Address Byte
5
A
Data Byte 3
5
4
A
4
A
12 13 14 15 16 17 18 19 20 21 22 23
4
3
MCP7952X/MCP7951X
12 13 14 15 16 17 18 19 20 21 22 23
A
3
A
36 37
3
applied to the chip, the address counter will roll back to
the first address of the page and overwrite any data that
previously existed in those locations.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to
detailed illustrations on the byte write sequence and
the page write sequence, respectively. While the non-
volatile memory write is in progress, the STATUS reg-
ister may be read to check the status of the WIP, WEL,
BP1 and BP0 bits. Attempting to read a memory array
location will not be possible during a write cycle. Polling
the WIP bit in the STATUS register is recommended in
order to determine if a write cycle is in progress. When
the nonvolatile memory write cycle is completed, the
write enable latch is reset.
2
A
A
2
2
1
A
A
38 39
1
1
0
A
0
0
7
7
6
6
5
7
Data Byte 1
Figure 3-2
Data Byte n (8 max)
Data Byte
5
6
4
4
5
3
3
4
2
and
2
3
1
Figure 3-3
2
DS22300A-page 9
1
0
1
0
0
for more
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