AC244027 Microchip Technology, AC244027 Datasheet - Page 194

• Manufacturer Part Number: AC244027
• Description: Processor Extension Pak (PIC16LF727-ICE) 200K Device Emulator - Debugger Accesso
• Manufacturer: Microchip Technology
• Series: -r

Specifications of AC244027

• Accessory Type: Debug Interface Module
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: PIC16F727

PIC16F72X/PIC16LF72X
19.2
When global interrupts are disabled (GIE cleared) and
any interrupt source has both its interrupt enable bit
and interrupt flag bit set, one of the following will occur:
• If the interrupt occurs before the execution of a
• If the interrupt occurs during or after the
FIGURE 19-1:
TABLE 19-1:
DS41341E-page 194
Name
IOCB
INTCON
PIE1
PIE2
PIR1
PIR2
Legend:
Instruction Flow
(INTCON reg.)
SLEEP instruction, the SLEEP instruction will
complete as a NOP. Therefore, the WDT and WDT
prescaler and postscaler (if enabled) will not be
cleared, the TO bit will not be set and the PD bit
will not be cleared.
execution of a SLEEP instruction, the device will
immediately wake-up from Sleep. The SLEEP
instruction will be completely executed before the
wake-up. Therefore, the WDT and WDT prescaler
and postscaler (if enabled) will be cleared, the TO
bit will be set and the PD bit will be cleared.
(INTCON reg.)
Note
INTF flag
GIE bit
Instruction
Fetched
Instruction
Executed
OSC1
CLKOUT
INT pin
1:
2:
3:
4:
Wake-up Using Interrupts
PC
(1)
x = unknown, u = unchanged, – = unimplemented, read as ‘0’. Shaded cells are not used in Power-Down mode.
XT, HS or LP Oscillator mode assumed.
T
GIE = 1 assumed. In this case after wake-up, the processor jumps to 0004h. If GIE = 0, execution will continue in-line.
CLKOUT is not available in XT, HS, LP or EC Oscillator modes, but shown here for timing reference.
TMR1GIE
TMR1GIF
(4)
OST
IOCB7
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
Inst(PC) = Sleep
Bit 7
GIE
—
—
Inst(PC - 1)
= 1024 T
SUMMARY OF REGISTERS ASSOCIATED WITH POWER-DOWN MODE
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
IOCB6
OSC
Bit 6
PEIE
ADIE
ADIF
—
—
(drawing not to scale). This delay does not apply to EC and RC Oscillator modes.
Inst(PC + 1)
Sleep
PC + 1
IOCB5
Bit 5
RCIE
RCIF
T0IE
—
—
Processor in
IOCB4
Bit 4
INTE
TXIE
TXIF
Sleep
—
—
PC + 2
IOCB3
SSPIE
SSPIF
T
Bit 3
RBIE
OST (2)
—
—
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Interrupt Latency
CCP1IE
CCP1IF
Inst(PC + 2)
Inst(PC + 1)
IOCB2
Bit 2
T0IF
Even if the flag bits were checked before executing a
SLEEP instruction, it may be possible for flag bits to
become set before the SLEEP instruction completes.
To determine whether a SLEEP instruction executed,
test the PD bit. If the PD bit is set, the SLEEP instruction
was executed as a NOP.
To ensure that the WDT is cleared, a CLRWDT instruction
should be executed before a SLEEP instruction.
—
—
PC + 2
TMR2IE
TMR2IF
IOCB1
Bit 1
INTF
—
—
(3)
Dummy Cycle
PC + 2
TMR1IE
CCP2IE
TMR1IF
CCP2IF
IOCB0
Bit 0
RBIF
© 2009 Microchip Technology Inc.
Dummy Cycle
Inst(0004h)
POR, BOR
0000 0000
0000 0000
0000 0000
---- ---0
0000 0000
---- ---0
0004h
Value on
Inst(0005h)
Inst(0004h)
other Resets
Value on all
0005h
0000 0000
0000 0000
0000 0000
---- ---0
0000 0000
---- ---0