AC244026 Microchip Technology, AC244026 Datasheet - Page 25
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AC244026
Manufacturer Part Number
AC244026
Description
Processor Extension Pak (PIC16F727-ICE) 200K Device Emulator - Debugger Accessor
Manufacturer
Microchip Technology
Series
-r
Datasheet
1.AC164112.pdf
(302 pages)
Specifications of AC244026
Accessory Type
Debug Interface Module
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
For Use With/related Products
PIC16LF727
- Current page: 25 of 302
- Download datasheet (5Mb)
TABLE 2-1:
© 2009 Microchip Technology Inc.
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend:
Note
Address
Bank 1
(2)
(2)
(2)
(2)
(3)
(1, 2)
(2)
1:
2:
3:
4:
5:
6:
INDF
OPTION_REG
PCL
STATUS
FSR
TRISA
TRISB
TRISC
TRISD
TRISE
PCLATH
INTCON
PIE1
PIE2
PCON
T1GCON
OSCCON
OSCTUNE
PR2
SSPADD
SSPMSK
SSPSTAT
WPUB
IOCB
TXSTA
SPBRG
APFCON
FVRCON
ADCON1
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are
transferred to the upper byte of the program counter.
These registers can be addressed from any bank.
These registers/bits are not implemented on PIC16F722/723/726/PIC16LF722/723/726 devices, read as ‘0’.
Accessible only when SSPM<3:0> = 1001.
Accessible only when SSPM<3:0> ≠ 1001.
This bit is always ‘1’ as RE3 is input only.
Name
—
—
—
—
(5)
(4)
PIC16F72X/PIC16LF72X SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter (PC) Least Significant Byte
Indirect Data Memory Address Pointer
Timer2 Period Register
Synchronous Serial Port (I
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Unimplemented
TMR1GIE
TMR1GE
FVRRDY
TRISC7
TRISD7
WPUB7
TRISA7
TRISB7
IOCB7
RBPU
CSRC
BRG7
Bit 7
SMP
IRP
GIE
—
—
—
—
—
—
—
—
T1GPOL
INTEDG
TRISA6
TRISB6
TRISC6
TRISD6
WPUB6
FVREN
ADCS2
IOCB6
BRG6
PEIE
ADIE
Bit 6
CKE
RP1
TX9
—
—
—
—
—
—
—
TRISA5
TRISB5
TRISC5
TRISD5
WPUB5
T1GTM
2
2
ADCS1
IOCB5
IRCF1
TUN5
TXEN
BRG5
T0CS
C
C
RCIE
Bit 5
T0IE
RP0
D/A
—
—
—
—
™
™
—
—
mode) Address Register
mode) Address Mask Register
Write Buffer for the upper 5 bits of the Program Counter
T1GSPM
TRISC4
TRISD4
WPUB4
TRISA4
TRISB4
ADCS0
IOCB4
IRCF0
SYNC
BRG4
T0SE
TUN4
Bit 4
INTE
TXIE
TO
—
—
—
—
—
P
PIC16F72X/PIC16LF72X
TRISE3
T1GGO/
TRISC3
TRISD3
WPUB3
TRISA3
TRISB3
IOCB3
SSPIE
DONE
BRG3
TUN3
RBIE
Bit 3
ICSL
PSA
PD
—
—
—
—
—
—
S
(6)
TRISE2
T1GVAL
TRISC2
TRISD2
CCP1IE
WPUB2
TRISA2
TRISB2
IOCB2
BRGH
BRG2
TUN2
ICSS
Bit 2
T0IF
PS2
R/W
—
—
—
—
—
Z
(3)
TRISE1
ADFVR1
ADREF1
T1GSS1
TMR2IE
TRISA1
TRISB1
TRISC1
TRISD1
WPUB1
SSSEL
IOCB1
TRMT
BRG1
TUN1
INTF
Bit 1
POR
PS1
DC
UA
—
—
(3)
CCP2SEL ---- --00
TRISE0
T1GSS0
ADFVR0
ADREF0
TMR1IE
CCP2IE
TRISA0
TRISB0
TRISC0
TRISD0
WPUB0
IOCB0
TUN0
BRG0
TX9D
RBIF
Bit 0
BOR
PS0
BF
—
C
(3)
DS41341E-page 25
xxxx xxxx
1111 1111
0000 0000
0001 1xxx
xxxx xxxx
1111 1111
1111 1111
1111 1111
1111 1111
---- 1111
---0 0000
0000 000x
0000 0000
---- ---0
---- --qq
0000 0x00
--10 qq--
--00 0000
1111 1111
0000 0000
1111 1111
0000 0000
1111 1111
0000 0000
0000 -010
0000 0000
q0-- --00
0000 --00
POR, BOR
Value on:
—
—
—
—
125,41
127,41
177,41
188,41
187,41
154,41
156,41
109,41
105,41
31,40
28,41
30,40
27,40
31,40
54,41
63,41
73,41
81,41
85,41
30,40
46,40
47,41
48,41
29,41
91,41
92,41
64,41
64,41
53,41
Page
—
—
—
—
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