CLC5526PCASM/NOPB National Semiconductor, CLC5526PCASM/NOPB Datasheet - Page 8

• Manufacturer Part Number: CLC5526PCASM/NOPB
• Manufacturer: National Semiconductor

Specifications of CLC5526PCASM/NOPB

• Lead Free Status / Rohs Status: Compliant

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Applications
DESCRIPTION
The CLC5526 is a digitally programmable, variable gain
amplifier with the following features:
Please refer to Figure 1 for a representative block diagram.
GAIN SELECTION
Gain levels can be decreased from the maximum value in
−6dB steps via the 3-bit digital inputs. Table 1 shows the gain
selection truth table for a 1000Ω differential load.
Gain settings can be calculated as follows:
Gain selection has two modes: Transparent or latched, de-
pending on the LATCH input. If the LATCH input is held
LOW, then the device is in the transparent mode. Changes
on data inputs will result in direct changes to the gain setting.
• 8 gain settings ranging from −12 to +30 dB in 6dB steps
• Differential inputs and outputs (externally AC coupled)
• Self biased input common-mode voltage
• 3-bit parallel digital control
• Single +5V supply
• Low-Power standby mode
GAIN = −12 dB + (Gain Word)
Word
Gain
0
1
2
3
4
5
6
7
TABLE 1. Gain Selection Truth Table
FIGURE 1. CLC5526 Block Diagram
MSB
0
0
0
0
1
1
1
1
ISB
0
0
1
1
0
0
1
1
*
6.02 dB
LSB
0
1
0
1
0
1
0
1
Gain (dB)
−12
+12
+18
+24
+30
−6
+6
01501616
0
8
Input data will be latched upon the LOW to HIGH transition of
LATCH. While LATCH is HIGH, digital data will be ignored
until LATCH is strobed low again.
Note: Upon power-up the analog inputs are disconnected
from the internal amplifier. LATCH will need to be strobed
LOW before an analog output will be present!
DIFFERENTIAL I/O CONSIDERATIONS
Analog inputs and outputs need to be AC coupled to prevent
DC loading of the common-mode voltages. If driving the
CLC5526 from a single-ended 50Ω source is required, a 1:2
transformer should be used to generate the differential in-
puts. As the differential input impedance of the CLC5526 is
200Ω, the 1:4 impedance ratio will allow for optimum match-
ing to the 50Ω source. The secondary outputs of the trans-
former should be AC coupled to the CLC5526 analog inputs,
while the secondary center tap of the transformer should be
directly connected to the system ground.
The CLC5526 is designed to drive differential circuits, such
as the CLC5957 Analog to Digital convertor. Figure 2 below
shows a typical application of the CLC5526.
DRIVING LOADS
Actual gain of the CLC5526 will vary with the output load.
The device is designed to provide +30 dB maximum gain
with a 1000Ω differential load.
Each output of the CLC5526 contains an internal 300Ω
resistor to the V
this in account with a given external load resistor. The effec-
tive load resistance can be used with the following equation
to calculate max gain values.
Chart 1 shows maximum gain values over output load. Re-
sistor values are for differential loads.
A
Where: R
R
V
int
= 20 log (0.0843
= 600Ω differential
FIGURE 2. Differential I/O Connections
leff
= R
CC
int
rail. Actual gain calculations need to take
|| R
*
R
ext(diff)
leff
)
01501617