PPC405GP-3BE266C Applied Micro Circuits Corporation, PPC405GP-3BE266C Datasheet - Page 48

• Manufacturer Part Number: PPC405GP-3BE266C
• Manufacturer: Applied Micro Circuits Corporation

Specifications of PPC405GP-3BE266C

• Family Name: 405GP
• Device Core: PowerPC
• Device Core Size: 32b
• Frequency (max): 266MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2.5V
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 456
• Package Type: EBGA
• Lead Free Status / Rohs Status: Not Compliant

405GP – Power PC 405GP Embedded Processor
I/O Specifications—133 and 200MHz
Notes:
1. The SDRAM command interface is configurable through SDRAM0_TR[LDF] to provide a 2 to 4 cycle delay before the
2. SDRAM I/O timings are specified relative to a MemClkOut terminated into a lumped 10pF load.
3. SDRAM interface hold times are guaranteed at the PPC405GP package pin. System designers must use the PPC405GP
4. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 0.8ns.
5. I/O H is specified at 2.4 V and I/O L is specified at 0.4 V.
48
SDRAM Interface
BA1:0
BankSel3:0
CAS
ClkEn0:1
DQM0:3
DQMCB
ECC0:7
MemAddr12:0
MemData0:31
RAS
WE
External Slave Peripheral Interface
DMAAck0:3
DMAReq0:3
EOT0:3/TC0:3
PerAddr0:31
PerBLast
PerCS0
PerCS1:7[GPIO10:16]
PerData0:31
PerOE
PerPar0:3
PerR/W
PerReady
PerWBE0:3
External Master Peripheral Interface
BusReq
ExtAck
ExtReq
ExtReset
HoldAck
HoldPri
HoldReq
PerClk
PerErr
command is used by SDRAM.
IBIS model (available from www.amcc.com) to ensure their clock distribution topology minimizes loading and reflections,
and that the relative delays on clock wiring do not exceed the delays on other SDRAM signal wiring.
Signal
Setup Time
(T
IS
na
na
na
na
na
na
na
na
na
na
dc
na
na
na
na
na
na
na
2
2
5
4
4
6
4
4
9
3
5
4
5
3
min)
Input (ns)
Hold Time
(T
IH
na
na
na
na
na
na
na
na
na
na
dc
na
na
na
na
na
na
na
1
1
1
1
1
1
1
1
1
1
1
1
1
1
min)
Valid Delay
(T
OV
7.5
6.2
7.5
5.2
6.1
6.2
6.2
7.6
6.3
7.5
7.5
0.9
na
10
10
10
na
na
na
na
na
8
8
8
8
8
8
8
8
7
8
8
max)
Output (ns)
Hold Time
(T
OH
0.7
na
na
na
na
na
na
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
min)
(minimum)
Output Current (mA)
I/O H
19
19
19
40
19
19
19
19
19
19
19
12
na
12
19
12
12
19
12
19
12
na
12
12
12
na
19
12
na
na
19
na
Revision 2.05 – August 19, 2008
(minimum)
I/O L
12
12
12
25
12
12
12
12
12
12
12
na
12
12
12
na
na
12
na
na
12
na
8
8
8
8
8
8
8
8
8
8
Data Sheet
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
MemClkOut
PLB Clk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
PerClk
Clock
Notes
1, 2
1, 2
1, 2
1, 2
1, 2
AMCC
2
2
2
2
2
2
4