HI-8591PST-40 Holt Integrated Circuits, HI-8591PST-40 Datasheet

HI-8591PST-40

Manufacturer Part Number

HI-8591PST-40

Description

Manufacturer

Holt Integrated Circuits

Datasheet

1.HI-8591PST-40.pdf (7 pages)

Specifications of HI-8591PST-40

Operating Temperature Classification

Military

Operating Temperature (max)

125C

Package Type

SOIC N

Rad Hardened

Lead Free Status / Rohs Status

Not Compliant

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DESCRIPTION

The HI-8591 is an ARINC 429 bus interface receiver

designed to operate from a single 3.3 V or 5 V supply. The

part is designed with high-impedance inputs to minimize

bus loading, and has an exceptional input common-mode

performance in excess of +/- 30V, making it immune to

ground offsets around the aircraft. The RINA and RINB

inputs of the standard HI-8591 may be connected directly

to the ARINC 429 bus. To enable external lightning protec-

tion circuitry to be added, the HI-8591-40 variant is avail-

able. The HI-8591-40 requires only the addition of external

40 K , ¼ watt resistors in series with RINA and RINB to

allow the part to meet the lightning protection requirements

of DO-160D level 3.

The typical 10 volt differential ARINC 429 signal is trans-

lated and input to a window comparator and latch. The

comparator levels are set just below the standard 6.5 volt

minimum ARINC data threshold and just above the stan-

dard 2.5 volt maximum ARINC null threshold.

The TESTA and TESTB inputs bypass the analog inputs for

testing purposes. Also if TESTA and TESTB are both taken

high, the digital outputs are forced to zero.

See Holt Application Note AN-300 for more information on

lightning protection.

FEATURES

(DS8591, Rev. E)

March 2007

3.3V single rail supply voltage

+/-30 V common-mode performance

>140 KOhm input impedance

Lightning protection simplified with the

Receiver input hysteresis at least 2 volt

Test inputs bypass analog inputs and

ARINC 429 line receiver interface in a

small outline package

ability to add 40 KOhm external series

resistors

force digital outputs to a one, zero or

null state

HOLT INTEGRATED CIRCUITS

www.holtic.com

PIN CONFIGURATIONS

SUPPLY VOLTAGES

FUNCTION TABLE

PIN DESCRIPTION TABLE

HI-8591PCI, HI-8591PCT, HI-8591PCI-40 & HI-8591PCT-40

vcc

SYMBOL

-1.25V to 1.25V

-3.25V to -6.5V

VCC

TESTA

RINB

RINA

GND

ROUTA

ROUTB

TESTB

3.25V to 6.5V

HI-8591PSI-40, HI-8591PST-40 & HI-8591PSM-40

RINA

= 3.3V

TESTA - 2

HI-8591PSI, HI-8591PST & HI-8591PSM

RINB - 3

RINA - 4

VCC - 1

16- pin 4mm x 4mm Chip-scale package

8 - PIN PLASTIC NARROW BODY SOIC

SUPPLY

LOGIC INPUT

ARINC INPUT

POWER

LOGIC OUTPUT

LOGIC INPUT

FUNCTION

± 10%,

TESTA 1

RINB 2

RINA 3

-1.25V to 1.25V

-3.25V to -6.5V

3.25V to 6.5V

NC 4

RINB

5.0V ± 10%

3.3V or 5V SUPPLY

CMOS

RECEIVER B INPUT

RECEIVER A INPUT

GROUND

RECEIVER CMOS OUTPUT A

RECEIVER CMOS OUTPUT B

CMOS

DESCRIPTION

HI-8591

TESTA

Line Receiver

12 ROUTB

11 NC

10 ROUTA

ARINC 429

TESTB ROUTA ROUTB

8 - TESTB

7 - ROUTB

6 - ROUTA

5 - GND

03/07

Related parts for HI-8591PST-40

HI-8591PST-40 Summary of contents

Page 1

... Rev. E) PIN CONFIGURATIONS VCC - 1 TESTA - 2 RINB - 3 RINA - 4 HI-8591PSI, HI-8591PST & HI-8591PSM HI-8591PSI-40, HI-8591PST-40 & HI-8591PSM- PIN PLASTIC NARROW BODY SOIC TESTA 1 HI-8591PCI, HI-8591PCT, HI-8591PCI-40 & HI-8591PCT-40 16- pin 4mm x 4mm Chip-scale package SUPPLY VOLTAGES vcc = 3.3V ± 10%, ...

Page 2

... One or Zero input sets the latches. The logic at the output is controlled by the test signal which is generated by the logical OR of the TESTA and TESTB pins. If TESTA and TESTB are both One, the HI- 8591 outputs are pulled low. This allows the digital out- puts of a transmitter to be connected to the test inputs through control logic for system self-test purposes ...

Page 3

... RECOMMENDED OPERATING CONDITIONS Supply Voltages VCC..............................3. ± 10% Temperature Range Industrial Screening........-40°C to +85°C Hi-Temp Screening.......-55°C to +125°C Military Screening.........-55°C to +125°C NOTE: Stresses above absolute maximum ratings or outside recommended operating con- ditions may cause permanent damage to the device. These are stress ratings only. Opera- tion at the limits is not recommended ...

Page 4

... Receiver propagation delay Output high to low Output low to high TEST pin propagation delay Output high to low Output low to high Receiver output transition times Output high to low Output low to high Input capacitance (1) ARINC differential ARINC single ended to Ground Logic Notes: 1. Guaranteed but not tested ...

Page 5

... TO +125°C M YES PACKAGE DESCRIPTION 16 PIN PLASTIC CHIP SCALE (16PCS) not available with “M” flow 8 PIN PLASTIC DIP (8P) not available with “M” flow 8 PIN PLASTIC NARROW BODY SOIC (8HN) 8 PIN CERDIP (8D) not available Pb-free HOLT INTEGRATED CIRCUITS ...

Page 6

... BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) HI-8591 PACKAGE DIMENSIONS .154 ± .004 (3.90 ± .09) .0165 ± .003 (.419 ± .089) 0° ...

Page 7

... BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 16-PIN PLASTIC CHIP-SCALE PACKAGE 4.00 BSC Top View 4.00 BSC 1.00 max HI-8591 PACKAGE DIMENSIONS .385 ±.015 (9.799 ± ...

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