K4S641632D-LL60 Samsung Semiconductor, K4S641632D-LL60 Datasheet - Page 7

• Manufacturer Part Number: K4S641632D-LL60
• Manufacturer: Samsung Semiconductor
• Type: SDRAMr

Specifications of K4S641632D-LL60

• Organization: 4Mx16
• Density: 64Mb
• Address Bus: 14b
• Access Time (max): 5.5ns
• Maximum Clock Rate: 166MHz
• Operating Supply Voltage (typ): 3.3V
• Package Type: TSOP-II
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Supply Current: 160mA
• Pin Count: 54
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

AC OPERATING TEST CONDITIONS
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Notes :
K4S641632D
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Notes :
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to active delay
Last data in to new col. address Delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output
data
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -55/60/70/80/1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
1. The DC/AC Test Output Load of K4S641632D-55/60 is 30pF.
2. The VDD condition of K4S641632D-55/60 is 3.135V~3.6V.
(Fig. 1) DC output load circuit
and then rounding off to the next higher integer.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.
Output
Parameter
Parameter
870
CAS latency=3
CAS latency=2
3.3V
1200
50pF
t
t
t
t
t
t
t
t
t
RAS
Symbol
RRD
RCD
t
RAS
t
CCD
RDL
DAL
CDL
BDL
RP
RC
V
V
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
OH
OL
(DC) = 0.4V, I
(DC) = 2.4V, I
(V
DD
= 3.3V
16.5
16.5
38.5
-55
11
55
OL
OH
= 2mA
= -2mA
0.3V, T
-60
12
18
18
42
60
A
= 0 to 70 C)
-70
14
20
20
49
68
See Fig. 2
-
tr/tf = 1/1
2.4/0.4
Value
2CLK + 20ns
1.4
1.4
Version
100
-75
15
20
20
45
65
Output
2
1
1
1
2
(Fig. 2) AC output load circuit
-80
16
20
20
48
68
Rev. 0.3 June 2000
-1H
Z0 = 50
20
20
20
50
70
CMOS SDRAM
1
-1L
20
20
20
50
70
Unit
Vtt = 1.4V
ns
Unit
CLK
CLK
CLK
CLK
V
V
V
50
50pF
ns
ns
ns
ns
us
ns
ea
-
Note
2,5
1
1
1
1
1
5
2
2
3
4