DS90C241QVS National Semiconductor, DS90C241QVS Datasheet - Page 12

• Manufacturer Part Number: DS90C241QVS
• Manufacturer: National Semiconductor

Specifications of DS90C241QVS

• Number Of Elements: 1
• Number Of Receivers: 24
• Number Of Drivers: 1
• Input Type: CMOS/TTL
• Operating Supply Voltage (typ): 3.3V
• Output Type: Serializer
• Differential Output Voltage: 1.2V
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

www.national.com
LVCMOS PARALLEL INTERFACE PINS
4-1,
48-44,
41-32,
29-25
10
CONTROL AND CONFIGURATION PINS
9
18
23
11
12
5
8
13
LVDS SERIAL INTERFACE PINS
20
19
POWER / GROUND PINS
22
21
16
17
14
15
30
31
7
6
42
Pin #
DS90C241 Serializer Pin Descriptions
DIN[23:0]
TCLK
TPWDNB
DEN
PRE
TRFB
VODSEL
DCAOFF
DCBOFF
RESRVD
DOUT+
DOUT−
VDDDR
VSSDR
VDDPT0
VSSPT0
VDDPT1
VSSPT1
VDDT
VSST
VDDL
VSSL
VDDIT
Pin Name
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVCMOS_I
LVDS_O
LVDS_O
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
I/O
Transmitter Parallel Interface Data Input Pins. Tie LOW if unused, do not float.
Transmitter Parallel Interface Clock Input Pin. Strobe edge set by TRFB configuration pin.
Transmitter Power Down Bar
TPWDNB = H; Transmitter is Enabled and ON
TPWDNB = L; Transmitter is in power down mode (Sleep), LVDS Driver D
in TRI-STATE stand-by mode, PLL is shutdown to minimize power consumption.
Transmitter Data Enable
DEN = H; LVDS Driver Outputs are Enabled (ON).
DEN = L; LVDS Driver Outputs are Disabled (OFF), Transmitter LVDS Driver D
are in TRI-STATE, PLL still operational and locked to TCLK.
Pre-emphasis Level Select
PRE = NC (No Connect); Pre-emphasis is Disabled (OFF).
Pre-emphasis is active when input is tied to VSS through external resistor R
determines pre-emphasis level. Recommended value R
3 kΩ
Transmitter Clock Edge Select Pin
TRFB = H; Parallel Interface Data is strobed on the Rising Clock Edge.
TRFB = L; Parallel Interface Data is strobed on the Falling Clock Edge
VOD Level Select
VODSEL = L; LVDS Driver Output is
VODSEL = H; LVDS Driver Output is
For normal applications, set this pin LOW. For long cable applications where a larger VOD is
required, set this pin HIGH.
Reserved. This pin MUST be tied LOW.
Reserved. This pin MUST be tied LOW.
Reserved. This pin MUST be tied LOW.
Transmitter LVDS True (+) Output.
This output is intended to be loaded with a 100Ω load to the D
be AC Coupled to this pin with a 100 nF capacitor.
Transmitter LVDS Inverted (-) Output
This output is intended to be loaded with a 100Ω load to the D
be AC Coupled to this pin with a 100 nF capacitor.
Analog Voltage Supply, LVDS Output Power
Analog Ground, LVDS Output Ground
Analog Voltage supply, VCO Power
Analog Ground, VCO Ground
Analog Voltage supply, PLL Power
Analog Ground, PLL Ground
Digital Voltage supply, Tx Serializer Power
Digital Ground, Tx Serializer Ground
Digital Voltage supply, Tx Logic Power
Digital Ground, Tx Logic Ground
Digital Voltage supply, Tx Input Power
12
≈
≈
±400 mV (R
±750 mV (R
Description
L
L
= 100Ω)
= 100Ω)
PRE
≥
OUT+
OUT-
3 kΩ; I
pin. The interconnect should
pin. The interconnect should
max
= [(1.2/R)*20], R
OUT
PRE
(+/-) Outputs are
OUT
. Resistor value
(+/-) Outputs
min
=