A3PN030-ZQNG48I Actel, A3PN030-ZQNG48I Datasheet - Page 9

• Manufacturer Part Number: A3PN030-ZQNG48I
• Manufacturer: Actel

Figure 1-4 • ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250)
Figure 1-5 • VersaTile Configurations
X1
X2
X3
LUT-3 Equivalent
LUT-3
The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input
logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate
flash switch interconnections. The versatility of the ProASIC3 nano core tile as either a three-input
lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the
FPGA fabric. The VersaTile capability is unique to the Actel ProASIC3 family of third-generation
architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.
Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable
interconnect programming. Maximum core utilization is possible for virtually any design.
In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)
programming of ProASIC3 nano devices via an IEEE 1532 JTAG interface.
VersaTiles
The ProASIC3 nano core consists of VersaTiles, which have been enhanced beyond the ProASIC
core tiles. The ProASIC3 nano VersaTile supports the following:
Refer to
Decryption
ISP AES
•
•
•
•
Y
All 3-input logic functions—LUT-3 equivalent
Latch with clear or set
D-flip-flop with clear or set
Enable D-flip-flop with clear or set
Figure 1-5
for VersaTile configurations.
D-Flip-Flop with Clear or Set
User Nonvolatile
Data
CLK
CLR
FlashROM
Bank 0
Bank 2
D-FF
A dv a n c e v 0. 6
Y
Charge Pumps
Enable D-Flip-Flop with Clear or Set
Enable
Data
CLK
CLR
ProASIC3 nano Device Overview
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block
CCC
I/Os
VersaTile
D-FF
Y
PLUS®
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