A3PE-BRD600-SKT MICROSEMI, A3PE-BRD600-SKT Datasheet - Page 22
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A3PE-BRD600-SKT
Manufacturer Part Number
A3PE-BRD600-SKT
Description
MCU, MPU & DSP Development Tools ProASIC3/E Starter Kit
Manufacturer
MICROSEMI
Datasheet
1.A3PE-BRD600-SKT.pdf
(106 pages)
Specifications of A3PE-BRD600-SKT
Processor To Be Evaluated
ProASIC3/E
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Hardware Components
22
Also note that the V
required in ProASIC3 (LVDS only available in A3P250 and larger) and ProASIC3E (LVDS available in all devices) for
LVDS signaling.
Refer to the PCB layout,
7
8
9
10
11
12
13
14
30
31
37
38
42
43
44
45
Notes:
1. Pin names are valid only for the A3PE600-PQ208 part. They are not correct for use with an
2. J40 – RJ45 connector is referred as CAT 5E PRIMARY connector.
3. J41 – RJ45 connector is referred as CAT 5E SECONDARY connector
FPGA Pin No.
A3P250.
CCI
and VMV voltages of Bank6 and Bank7 (west side) are connected to a fixed 2.5 volts, which is
Figure 2-1 on page
FPGA I/O Pin Name
GAC2/IO132PDB7V1
IO132NDB7V1
IO130PDB7V1
IO130NDB7V1
IO127PDB7V1
IO127NDB7V1
IO126PDB7V0
IO126NDB7V0
GFA2/IO117PDB6V1
IO117NDB6V1
IO112PDB6V1
IO112NDB6V1
IO106PDB6VO
IO106NDB6V0
GEC1/IO104PDB6V0
GEC0/IO104NDB6VO
Table 2-7 · FPGA – LVDS I/O Pin Details
10, for the location of J40 and J41 connectors on the PA3 Evaluation board.
1
Signal Name
ProASIC3/E Starter Kit User’s Guide and Tutorial
TX1+
TX1–
TX2+
TX2–
RX1–
RX2–
TX3+
TX3–
TX4+
TX4–
RX3–
RX4–
RX1+
RX2+
RX3+
RX4+
CAT 5E – PRI –1
CAT 5E – PRI –2
CAT 5E – PRI – 5
CAT 5E – PRI – 4
CAT 5E – PRI –3
CAT 5E – PRI – 6
CAT 5E – PRI – 7
CAT 5E – PRI – 8
CAT 5E – SEC –3
CAT 5E – SEC –6
CAT 5E – SEC – 7
CAT 5E – SEC – 8
CAT 5E – SEC –1
CAT 5E – SEC – 2
CAT 5E – SEC – 5
CAT 5E – SEC – 4
Connector
CAT5E
Pin No.
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