PEB24901HV12 Lantiq, PEB24901HV12 Datasheet - Page 25

• Manufacturer Part Number: PEB24901HV12
• Manufacturer: Lantiq

Specifications of PEB24901HV12

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Semiconductor Group
Table 4
MONITOR Command to set the Driver pins (Hexadecimal Addresses)
Hexadecimal
81 7x
3.2.1.2.4 Reading the Status Pins
Each channel owns two status pins ST
0, 1 specifies the pin. Their logical values are reported to the Monitor channel. Any
change at one of the two pins causes a two-byte Monitor message to be issued
automatically giving the state of both status pins. Additionally, the Quad IEC DFE-T will
issue the state of the two pins upon request . The request is given by a two-byte Monitor
command .
The ST
Table 5
MONITOR Commands to read Status pins
Hexadecimal
81 00
88 0x
3.2.2 Interface to the Analog Front End
The interface to the PEB 24902 Quad IEC AFE is a serial interface at the pins SDX and
SDR. On SDX and SDR transmit and receive data is exchanged as well as control
information for the start-up procedure. The ADC output from the Quad IEC AFE is
transferred to the Quad IEC DFE-T on the signals PDM0..PDM3. The timing of all signals
is based on the 15.36 MHz clock which is provided by the Quad IEC AFE.
The transmit data, powerup/down, range function and analog loopback are transferred
on SDX, and the level status on SDR for all line ports. Eight time slots contain the data
for up to eight line ports. The Quad IEC DFE-T uses four of them. The allocation of these
time slots is done by the nineth time slot, a 24 bit synch. word on SDX, that consists of
all ZEROs. The other time slots with transmission data start with a ONE. Therefore the
first ONE after 24 subsequent ZEROs is the first bit of time slot no. 0. This information is
also used to determine the status of synchronisation of the digital interface after reset.
The transmit pulses have to be disclosed to the Quad IEC AFE with a period of 120 kHz.
This defines the period of the SDX-frame. The 128 available bits during a 120 kHz
period (related to the 15.36 MHz clock) are divided into the 9 slots of which 8 slots are
ij
pins have to be tied to either VDD or GND, if not used.
Binary
1000 0001 0111 D C B A
Binary
1000 0001 0000 0000
1000 1000 0000 00 ST
ij
1
, where i = 0,1, 2, 3 denotes the channel and j =
ST
24
0
Request Status
Command
set Pins DiA, DiB, DiC, DiD
Command
Report Status of ST
i1
ST
PEB 24901
i0
02.95