PSB21384HV13NP Lantiq, PSB21384HV13NP Datasheet - Page 180

• Manufacturer Part Number: PSB21384HV13NP
• Manufacturer: Lantiq

Specifications of PSB21384HV13NP

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Data Sheet
5.1
5.1.1
The DPLL only readjusts with each received F/L edge of the S interface.
If the receiver has not yet synchronized the DPLL will adjust in one step.
5.1.2
The S transmit clock is derived from the S receive clock.
5.1.3
Jitter on the MCLK output is directly related to the crystal tolerance. Only clock dividers
are involved.
Figure 90
Clock waveforms
Jitter
Jitter on IOM-2
Jitter on S
Jitter on MCLK
FSC
DCL
BCL
170
Clock Generation
PSB 21381/2
PSB 21383/4
2001-03-12