PSB21384HV13XT Lantiq, PSB21384HV13XT Datasheet - Page 94
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PSB21384HV13XT
Manufacturer Part Number
PSB21384HV13XT
Description
Manufacturer
Lantiq
Datasheet
1.PSB21384HV13XT.pdf
(270 pages)
Specifications of PSB21384HV13XT
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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Data Sheet
2.3.7.1.5 C/I Indications
Indication
Deactivation Request
Reset
Test mode 1
Test mode 2
Resynchronization
during level detect
Power up
Activation request
Activation request loop ARL
Far-end-code-violation CVR
Activation indication
loop
Activation indication
with priority class 8
Activation indication
with priority class 10
Deactivation
confirmation
DR
RES
RSY
PU
AR
AIL
AI8
AI10
DC
Abbr. Code Remark
TM1
TM1
0000 Deactivation request via S/T-interface if left
0001 Reset acknowledge
0010 TM1 acknowledge
0010 TM2 acknowledge
0100 Signal received, receiver not synchronous
0111 IOM-2 interface clocking is provided
1000 Info 2 received
1010 Internal or external loop A closed
1011 Illegal code violation received. This function
1110 Internal or external loop A activated
1100 Info 4 received,
1101 Info 4 received,
1111 Clocks will be disabled if CFS bit of register
from F7/F8
has to be enabled by setting the EN_FECV bit
of register TR_CONF0 (see chapter 7.2.1).
D-channel priority is 8 or 9.
D-channel priority is 10 or 11.
MODE1 is set to ’1’ (see chapter 7.2.12),
quiescent state
84
PSB 21381/2
PSB 21383/4
Interfaces
2001-03-12
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