MC145572ACR2 Freescale Semiconductor, MC145572ACR2 Datasheet - Page 53
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MC145572ACR2
Manufacturer Part Number
MC145572ACR2
Description
Manufacturer
Freescale Semiconductor
Datasheet
1.MC145572ACR2.pdf
(264 pages)
Specifications of MC145572ACR2
Number Of Line Interfaces
1
Control Interface
HDLC
Lead Free Status / Rohs Status
Compliant
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MOTOROLA
TRANSPARENT
U-LOOP 2B+D
U-INTERFACE
U-INTERFACE
U-LOOP 2B+D
B1 FROM THE
4.4.8
SWAP B1/B2
U-LOOP B1
U-LOOP B1
B1 TO THE
U-LOOP
BR7: IDL2 Configuration Register
This register contains IDL2 interface mode information. BR7 is cleared on Hardware Reset (RESET)
or Software Reset (NR0(b3)). All bits in this register are read/write. This register is replaced by Register
OR7 when BR10(b0) = 1.
BR15A Select
When set to 1, this bit causes Register BR15A to be substituted for Register BR15 in the SCP register
map. After any reset, this bit is cleared to 0.
GCI IN2/OUT2
This is a read–only/write–only bit. The write–only portion, OUT2, is cleared by hardware and software
resets. In full GCI mode, entered by holding the pin MCU/GCI low, the state of OUT2 is driven onto
a GCI mode dedicated output pin. However, if the GCI C/I channel decodes the input command DISS
to the MC145572, this same pin is forced high. When read (again, provided the MC145572 is in full
GCI mode), bit IN2 reflects the state of a GCI mode dedicated input pin. These pins may be used
for any purpose in a GCI application. See Chapter 3, Device Description , for more information. GCI
command LTD2 when active in LT mode or NTD2 when active in NT mode, sets OUT2 high.
BR7
a/b
b
a
B1
B2
Figure 4–2. IDL2 Interface Loopback Logic Diagram
BR15A
Select
b7
Freescale Semiconductor, Inc.
IDL2-LOOP 2B+D
rw
For More Information On This Product,
IDL2-LOOP B1
SWAP B1/B2
GCI IN2
OUT2
UB2
b6
UB1
Go to: www.freescale.com
wo
ro
B1
GCI IN1
B2
OUT1
BLOCK B1
b5
MC145572
wo
ro
UB1
UB2
Invert
IDL2
b4
b
a
rw
a/b
Free Run
IDL2
b3
LINK ACTIVE
LINK GOOD
UB2
rw
UD
UB1
IDL2 INVERT
B1
Speed
IDL2
b2
rw
M/S Invert
IDL2
IDL2-LOOP TRANSPARENT
b1
rw
ID2L-LOOP B1
IDL2-LOOP 2B+D
D in
IDL2 INVERT
IDL2
8/10
b0
rw
4–17
D out
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