PSB21150FV14XT Lantiq, PSB21150FV14XT Datasheet - Page 177

• Manufacturer Part Number: PSB21150FV14XT
• Manufacturer: Lantiq

Specifications of PSB21150FV14XT

• Number Of Line Interfaces: 1
• Control Interface: HDLC
• Lead Free Status / Rohs Status: Compliant

MDS2-0 Mode
1
1
1
Note: SAP1, SAP2: two programmable address values for the first received address
RAC ... Receiver Active
The D-channel HDLC receiver is activated when this bit is set to ’1’. If set to ’0’ the HDLC
data is not evaluated in the receiver.
DIM2-0 ... Digital Interface Modes
These bits define the characteristics of the IOM Data Ports (DU, DD). The DIM0 bit
enables/disables the collission detection. The DIM1 bit enables/disables the TIC bus
access. The effect of the individual DIM bits is summarized in the table below.
Data Sheet
1
1
0
byte (in the case of an address field longer than 1 byte);
SAPG = fixed value FC / FE
TEI1, TEI2: two programmable address values for the second (or the only, in the
case of a one-byte address) received address byte;
TEIG = fixed value FF
Two different methods of the high byte and/or low byte address comparison can
be selected by setting SAP1.MHA and/or SAP2.MLA.
0 Transparent
1 Transparent
1 Transparent
mode 0
mode 1
mode 2
Number
of
Address
Bytes
–
> 1
> 1
H
H
.
1.Byte
–
SAP1,SAP2,SAPG –
–
177
Address Comparison
Detailed Register Description
2.Byte
–
TEI1,TEI2,TEIG
PSB/PSF 21150
Remark
No
address
compare.
All frames
accepted.
High-byte
address
compare.
Low-byte
address
compare.
2003-01-30
IPAC-X