54ABT543W-QML National Semiconductor, 54ABT543W-QML Datasheet - Page 2

• Manufacturer Part Number: 54ABT543W-QML
• Manufacturer: National Semiconductor

Specifications of 54ABT543W-QML

• Logic Family: ABT
• Operating Supply Voltage (typ): 5V
• Propagation Delay Time: 7.4ns
• Number Of Elements: 1
• Number Of Channels: 8
• Input Logic Level: TTL
• Output Logic Level: TTL
• Output Type: 3-State
• Package Type: CPAK
• Polarity: Non-Inverting
• Logical Function: Latched Transceiver
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Technology: BiCMOS
• Operating Temp Range: -55C to 125C
• Operating Temperature Classification: Military
• Mounting: Surface Mount
• Additional Features: Latched Transceiver
• Pin Count: 24
• Lead Free Status / Rohs Status: Not Compliant

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Pin Descriptions
Functional Description
The ’ABT543 contains two sets of D-type latches, with sepa-
rate input and output controls for each. For data flow from A
to B, for example, the A to B Enable (CEAB ) input must be
low in order to enter data from the A port or take data from
the B port as indicated in the Data I/O Control Table. With
CEAB low, a low signal on (LEAB ) input makes the A to B
latches transparent; a subsequent low to high transition of
the LEAB line puts the A latches in the storage mode and
their outputs no longer change with the A inputs. With CEAB
and OEAB both low, the B output buffers are active and
reflect the data present on the output of the A latches.
Control of data flow from B to A is similar, but using the
CEBA , LEBA and OEBA .
Logic Diagram
OEAB , OEBA
LEAB , LEBA
CEAB , CEBA
A
B
0
0
–A
–B
Pin Names
7
7
Output Enable Inputs
Latch Enable Inputs
Chip Enable Inputs
Side A Inputs or
TRI-STATE Outputs
Side B Inputs or
TRI-STATE Outputs
2
Description
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
CEAB
H
X
L
X
L
Inputs
LEAB
H
X
X
X
L
Data I/O Control Table
OEAB
X
X
X
H
L
Latch Status
Transparent
Latched
Latched
10021803
—
—
Buffers
Output
Driving
High Z
High Z
—
—