SI5110-H-GL Silicon Laboratories Inc, SI5110-H-GL Datasheet - Page 28

• Manufacturer Part Number: SI5110-H-GL
• Description: IC TXRX SONET/SDH LP HS 99LFBGA
• Manufacturer: Silicon Laboratories Inc
• Series: SiPHY®r
• Type: Transceiverr

Specifications of SI5110-H-GL

• Package / Case: 99-LFBGA
• Number Of Drivers/receivers: 1/1
• Protocol: SONET/SDH
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Product: PHY
• Supply Voltage (max): 1.89 V, 3.47 V
• Supply Voltage (min): 1.71 V
• Supply Current: 0.7 A
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 20 C
• Mounting Style: SMD/SMT
• Maximum Power Dissipation: 1300 mW
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

S i 5 11 0
28
Number(s)
B1, C1
C10
D10
A10
B10
Pin
A8
A7
C8
D3
C7
C9
D9
A9
B9
C3
RXCLK1DSBL
RXCLK2DSBL
RXCLK2DIV
RXDOUT3+
RXDOUT3–
RXDOUT2+
RXDOUT2–
RXDOUT1+
RXDOUT1–
RXDOUT0+
RXDOUT0–
RXCLK2+,
RXCLK2–
RXDIN+,
RXDIN–
RXLOL
Name
I/O
O
O
O
I
I
I
I
Signal Level
High-Speed
Differential
LVTTL
LVTTL
LVTTL
LVTTL
LVDS
LVDS
Rev. 1.4
Differential Receiver Clock Output 2.
An auxiliary output clock is provided on this pin that is
equivalent to, or a submultiple of, the output word rate.
The divide factor used in generating RXCLK2 is set
via RXCLK2DIV.
RXCLK2 Clock Divider Select.
This input selects the divide factor used to generate
the RXCLK2 output. When this input is driven high,
RXCLK2 is equal to the output word rate on RXDOUT.
When driven low, RXCLK2 is 1/4th the output word
rate.
Note: This input has an internal pullup.
RXCLK1 Disable.
Setting this input low disables the RXCLK1 output.
This is used to save power in applications that do not
require the primary output clock.
Note: This input has an internal pullup.
RXCLK2 Disable.
Setting this input low disables the RXCLK2 output.
This saves power in applications that do not require
an auxiliary clock.
Note: This input has an internal pullup.
Differential Receive Data Input.
The receive clock and data signals RXCLK1,
RXCLK2, and RXDOUT[3:0] are recovered from the
high-speed data signal present on these pins.
Differential Parallel Receive Data Output.
The data recovered from the signal present on RXDIN
is demultiplexed and output as a 4-bit parallel word via
RXDOUT[3:0]. The bit order for demultiplexing is
selected by the RXMSBSEL input. The RXDOUT[3:0]
outputs are aligned to the rising edge of RXCLK1.
Receiver Loss-of-Lock.
This output is asserted (driven low) when the recov-
ered clock frequency deviates from the reference
clock by the amount specified in Table 5 on page 9.
Description