CAT150089SWI-G ON Semiconductor, CAT150089SWI-G Datasheet
CAT150089SWI-G
Specifications of CAT150089SWI-G
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CAT150089SWI-G Summary of contents
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Voltage Supervisor with 8-Kb and 16-Kb SPI Serial CMOS EEPROM FEATURES Precision Power Supply Voltage Monitor 5V, 3.3V, 3V & 2.5V systems 7 threshold voltage options Active High or Low Reset Valid reset guaranteed at V 10MHz SPI compatible 32-byte ...
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CAT15008, CAT15016 BLOCK DIAGRAM SO SCK ABSOLUTE MAXIMUM RATINGS Parameters Storage Temperature Voltage on Any Pin with Respect to Ground RELIABILITY CHARACTERISTICS Symbol Parameter (4) NEND Endurance TDR Data Retention D.C. OPERATING CHARACTERISTICS V = +2.5V to ...
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A.C. CHARACTERISTICS (MEMORY 2.5V to 5.5V -40°C to 85°C, unless otherwise specified Symbol Parameter f Clock Frequency SCK t Data Setup Time SU t Data Hold Time H t SCK High Time WH t ...
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CAT15008, CAT15016 ELECTRICAL CHARACTERISTICS (SUPERVISORY FUNCTION Full range -40ºC to +85ºC unless otherwise noted. Typical values L/M/J versions 3.3V for T/S versions Symbol Parameter V Reset Threshold Voltage ...
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PIN DESCRIPTION ¯¯¯¯¯¯ RESET/RESET : Reset output is available in two versions: CMOS Active Low (CAT150xx9) and CMOS Active High (CAT150xx1). Both versions are push-pull outputs for high efficiency. SI: The serial data input pin accepts op-codes, addresses and data. ...
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CAT15008, CAT15016 Figure 2 shows the maximum pulse duration of negative-going V transients that do not cause a reset CC condition. As the amplitude of the transient goes further below the threshold (increasing V maximum pulse duration decreases. In this ...
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STATUS REGISTER The Status Register, as shown in Table 2, contains a number of status and control bits. ¯¯¯¯ (Ready) bit indicates whether the device is The RDY busy with a write operation. This bit is automatically set to 1 ...
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CAT15008, CAT15016 WRITE OPERATIONS The CAT15008/16 device powers up into a write disable state. The device contains a Write Enable Latch (WEL) which must be set before attempting to write to the memory array or to the status register. In ...
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Byte Write Once the WEL bit is set, the user may execute a write sequence, by sending a WRITE instruction, a 16-bit address and data as shown in Figure 6. Only 10 significant address bits are used by the CAT15008 ...
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CAT15008, CAT15016 Write Status Register The Status Register is written by sending a WRSR instruction according to timing shown in Figure 8. Only bits 2, 3 and 7 can be written using the WRSR command. Figure 8. WRSR Timing CS ...
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READ OPERATIONS Read from Memory Array To read from memory, the host sends a READ instruction followed by a 16-bit address (see Table 5 for the number of significant address bits). After receiving the last address bit, the CAT15008/16 will ...
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CAT15008, CAT15016 PACKAGE OUTLINE DRAWING SOIC 8-Lead 150 mil ( SYMBOL MIN A1 0.10 A 1.35 b 0.33 C 0.19 D 4.80 E 5. 0.25 L 0.40 q1 0° Notes: (1) All dimensions ...
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PACKAGE MARKING 8-LEAD SOIC 150XXZWI ○ 4YYWWA CSI = Catalyst Semiconductor, Inc Device Code (see Marking Code table below Supervisory Output Code (see Marking Code table below Temperature Range YY = Production Year WW ...
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... All packages are RoHS-compliant (Lead-free, Halogen-free). (2) The standard lead finish is NiPdAu pre-plated (PPF) lead frames. (3) The device used in the above example is a CAT150089SWI-GT3 (8Kb EEPROM, with Active Low CMOS Reset output, with a reset threshold between 2.85V - 3.00V, SOIC package, Industrial Temperature, NiPdAu, Tape and Reel. ...
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... Initial Issue 10-Nov-08 B Change logo and fine print to ON Semiconductor ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “ ...