MAX6897PAZT+T Maxim Integrated Products, MAX6897PAZT+T Datasheet - Page 5

• Manufacturer Part Number: MAX6897PAZT+T
• Description: Supervisory Circuits Adjustable Sequencer/Supervisor
• Manufacturer: Maxim Integrated Products

Specifications of MAX6897PAZT+T

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

µDFN
—
—
1
2
3
4
5
6
MAX6895/
MAX6897
SOT23
THIN
—
—
1
2
3
4
6
5
µDFN
_______________________________________________________________________________________
—
—
1
2
3
4
5
6
MAX6896/
MAX6898
PIN
SOT23
THIN
—
—
1
2
3
4
6
5
µDFN
—
—
1
2
3
4
5
6
MAX6899
Sequencing/Supervisory Circuits
SOT23
THIN
—
—
1
2
3
4
6
5
ENABLE
ENABLE
CDELAY
NAME
GND
OUT
OUT
V
IN
CC
Active-High Logic-Enable Input. Drive ENABLE low to
immediately deassert the output to its false state (OUT = low or
OUT = high) independent of V
ENABLE high to assert the output to its true state (OUT = high
or OUT = low) after the adjustable delay period (MAX689_A) or
a 150ns propagation delay (MAX689_P).
Active-Low Logic-Enable Input. Drive ENABLE high to
immediately deassert the output to its false state (OUT = low or
OUT = high) independent of V
ENABLE low to assert the output to its true state (OUT = high or
OUT = low) after the adjustable delay period (MAX689_A) or a
150ns propagation delay (MAX689_P).
Ground
High-Impedance Monitor Input. Connect IN to an external
resistive divider to set the desired monitored threshold. The
output changes state when V
falls below 0.495V.
Active-High Sequencer/Monitor Output, Push-Pull
(MAX6895/MAX6899) or Open-Drain (MAX6897). OUT is
asserted to its true state (OUT = high) when V
and the enable input is in its true state (ENABLE = high or
ENABLE = low) for the capacitor-adjusted delay period. OUT is
deasserted to its false state (OUT = low) immediately after V
drops below V
(ENABLE = low or ENABLE = high). The open-drain version
requires an external pullup resistor.
Acti ve- Low S eq uencer /M oni tor Outp ut, P ush- P ul l ( M AX 6896) or
O p en- D r ai n ( M AX 6898) . OU T i s asser ted to i ts tr ue state ( O UT =
l ow ) w hen V
( E N ABLE = hi g h or E NABLE = l ow ) after the C D E LAY ad j usted
ti m eout p er i od . O U T i s d easser ted to i ts fal se state ( O UT = hi g h)
i m m ed i atel y after V
i s i n i ts fal se state ( E N ABLE = l ow or E NABLE = hi g h) . The op en-
d r ai n ver si on r eq ui r es an exter nal p ul l up r esi stor .
Capacitor-Adjustable Delay. Connect an external capacitor
(C
ENABLE to OUT or ENABLE to OUT for A version devices)
delay period. t
fixed short delay (40µs, typ) for the output deasserting when V
falls below V
Supply Voltage Input. Connect a 1.5V to 5.5V supply to V
power the device. For noisy systems, bypass with a 0.1µF
ceramic capacitor to GND.
Ultra-Small, Adjustable
CDELAY
) from CDELAY to GND to set the IN to OUT (and
I N
TH
i s ab ove V
TH
DELAY
.
- 5mV or the enable input is in its false state
I N
d r op s b el ow V
= (C
T H
CDELAY
FUNCTION
and the enab l e i np ut i s i n i ts tr ue state
IN
IN
IN
rises above 0.5V and when V
. With V
. With V
x 4.0 x 10
T H
Pin Description
- 5m V or the enab l e i np ut
IN
IN
above V
above V
6
) + 40µs. There is a
IN
is above V
TH
TH
, drive
, drive
CC
TH
IN
to
IN
IN
5