71M6541D-IGT/F Maxim Integrated Products, 71M6541D-IGT/F Datasheet - Page 128

• Manufacturer Part Number: 71M6541D-IGT/F
• Description: PMIC Solutions Precision Energy Meter IC
• Manufacturer: Maxim Integrated Products
• Type: Metering SoCr

Specifications of 71M6541D-IGT/F

• Core: 8051
• Core Architecture: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 3 KB
• Device Million Instructions Per Second: 5 MIPS
• Interface Type: I2C, ICE, SPI, UART
• Maximum Clock Frequency: 5 MHz
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Programmable I/os: 30
• Number Of Timers: 2
• On-chip Adc: 22 bit
• Operating Supply Voltage: 3 V to 3.6 V
• Package / Case: LQFP-64
• Processor Series: 8051
• Program Memory Size: 32 KB
• Program Memory Type: Flash
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

given in
status flags for the preceding CE code pass (CE_BUSY interrupt). The significance of the bits in
CESTATUS is shown in
The CE is initialized by the MPU using CECONFIG
SAG_CNT, FREQSEL[1:0], EXT_PULSE, PULSE_SLOW and PULSE_FAST. The CECONFIG bit definitions are
128
CECONFIG
Address
CESTATUS
0x20
19:8
CE
7:6
31:4
bit
23
22
21
20
1. Default for CE41A01 (71M6541D/F or CE41A04 (71M6542F) CE code for use with local
2. Default for CE41B016201 and CE41B016601 codes that support the 71M6x01 remote
bit
3
2
1
0
Table
sensors.
sensors.
FREQSEL[1:0]
83.
CECONFIG
EXT_TEMP
EDGE_INT
SAG_CNT
SAG_INT
Reserved
Name
Name
Not Used
Not Used
SAG_B
SAG_A
Name
F0
Table
Table 83: CECONFIG (CE RAM 0x20) Bit Definitions
Table 81: CESTATUS (CE RAM 0x80) Bit Definitions
© 2008–2011 Teridian Semiconductor Corporation
81.
Default Description
0x00B0DB00
0x0030DB00
(0xFC)
252
Description
These unused bits are always zero.
F0 is a square wave at the exact fundamental input frequency.
This unused bit is always zero.
Normally zero. Becomes one when VB remains below SAG_THR for
SAG_CNT samples. Does not return to zero until VB rises above
SAG_THR.
Normally zero. Becomes one when VA remains below SAG_THR for
SAG_CNT samples. Does not return to zero until VA rises above
SAG_THR.
0
0
1
1
0
Data
Table 82: CECONFIG Register
When this bit is set, control of temperature compensation is
enabled for the 71M6x01 Isolated Sensor Interface.
When 1, the MPU controls temperature compensation via the
GAIN_ADJn registers (CE RAM 0x40-0x42), when 0, the CE is in
control.
When 1, XPULSE produces a pulse for each zero-crossing of
the mains phase selected by FREQSEL[1:0] , which can be used
to interrupt the MPU.
When 1, activates YPULSE output when a sag condition is
detected.
The number of consecutive voltage samples below SAG_THR
(CE RAM 0x24) before a sag alarm is declared. The default value
is equivalent to 100 ms.
monitor, sag detection, and for the zero crossing counter
(MAINEDGE_X, CE RAM 0x83).
*71M6542F only
FREQSEL[1:0] selects the phase to be used for the frequency
1
2
Description
See description of the CECONFIG bits in
Table
0
0
1
FREQ SEL[1:0]
(Table
83.
82). This register contains in packed form
X
0
1
Phase Selected
Not allowed
B*
A
v1.1