MAX5062CASA-T Maxim Integrated Products, MAX5062CASA-T Datasheet - Page 13

• Manufacturer Part Number: MAX5062CASA-T
• Description: MOSFET & Power Driver ICs 125V 2A Half-Bridge MOSFET Driver
• Manufacturer: Maxim Integrated Products
• Type: High Side/Low Sider

Specifications of MAX5062CASA-T

• Rise Time: 65 ns
• Fall Time: 65 ns
• Supply Voltage (min): 8 V
• Supply Current: 3 mA
• Maximum Power Dissipation: 1538.5 mW
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Bridge Type: Half Bridge
• Minimum Operating Temperature: - 40 C
• Number Of Drivers: 2
• Number Of Outputs: 2

where C
DL. V
frequency of the converter. P
sipated in the internal bootstrap diode. The internal
power dissipation reduces by P
bootstrap Schottky diode is used. The power dissipa-
tion in the internal boost diode (when driving a capaci-
tive load) will be the charge through the diode per
switching period multiplied by the maximum diode for-
ward voltage drop (V
The total power dissipation when using the internal
boost diode will be P
Schottky diode, will be P
dissipated in the device must be kept below the maxi-
mum of 1.951W for the 12-pin TQFN package, 1.5W for
the 8-pin SO with exposed pad, and 0.471W for the
regular 8-pin SO package at T
The MAX5062/MAX5063/MAX5064 drivers source and
sink large currents to create very fast rise and fall
edges at the gates of the switching MOSFETs. The high
di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled. Use
the following PC board layout guidelines when design-
ing with the MAX5062/MAX5063/MAX5064:
• It is important that the V
ground) or BST voltage (with respect to HS) does
not exceed 13.2V. Voltage spikes higher than 13.2V
DD
L
P
is the supply voltage and f
DIODE
is the combined capacitive load at DH and
=
______________________________________________________________________________________
C
DH
f
= 1V).
D
×
and, when using an external
D
(
V
DD
DD
- P
D
A
Layout Information
voltage (with respect to
−
DIODE
includes the power dis-
= +70°C ambient.
1
DIODE
)
×
SW
. The total power
f
SW
is the switching
, if an external
×
V
f
Half-Bridge MOSFET Drivers
• There are two AC current loops formed between the
• Solder the exposed pad of the TQFN (MAX5064) or
from V
device. Place one or more low ESL 0.1µF decou-
pling ceramic capacitors from V
(MAX5062/MAX5063) or to PGND (MAX5064), and
from BST to HS as close as possible to the part. The
ceramic decoupling capacitors should be at least
20 times the gate capacitance being driven.
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from gate
to source when the gate is being pulled low. The
active current loop is from the MOSFET driver output
(DL or DH) to the MOSFET gate, to the MOSFET
source, and to the return terminal of the MOSFET dri-
ver (either GND or HS). When the gate of the MOS-
FET is being pulled high, the active current loop is
from the MOSFET driver output, (DL or DH), to the
MOSFET gate, to the MOSFET source, to the return
terminal of the drivers decoupling capacitor, to the
positive terminal of the decoupling capacitor, and to
the supply connection of the MOSFET driver. The
decoupling capacitor will be either the flying capaci-
tor connected between BST and HS or the decou-
pling capacitor for V
minimize the physical distance and the impedance of
these AC current paths.
SO (MAX5062C/D and MAX5063C/D) package to a
large copper plane to achieve the rated power dissi-
pation. Connect AGND and PGND at one point near
V
125V/2A, High-Speed,
DD
’s decoupling capacitor return.
DD
to GND or BST to HS can damage the
DD
. Care must be taken to
DD
to GND
13