U6808B-MFPG3Y Atmel, U6808B-MFPG3Y Datasheet - Page 4

• Manufacturer Part Number: U6808B-MFPG3Y
• Description: MOSFET & Power Driver ICs Failsafe IC with Relay Driver
• Manufacturer: Atmel
• Type: Special Fail-Safer

Specifications of U6808B-MFPG3Y

• Supply Voltage (min): 4.5 V
• Supply Current: 15 mA
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5. Description of the Watchdog
5.1
5.2
5.3
5.4
4
Abstract
WDI Input
RCOSC Input
OSCERR Input
U6808B
Figure 5-1.
The microcontroller is monitored by a digital window watchdog which accepts an incoming trig-
ger signal of a constant frequency for correct operation. The frequency of the trigger signal can
be varied in a broad range as the watchdog's time window is determined by external R/C compo-
nents. The following description refers to the block diagram, see
The microcontroller has to provide a trigger signal with the frequency f
input. A positive edge of f
the up/down counter additionally. The latter one counts only from 0 to 3 or reverse. Each correct
trigger increments the up/down counter by 1, each wrong trigger decrements it by 1. As soon as
the counter reaches status 3 the RS flip-flop is set (see
signal is detected after 250 clocks of the internal watchdog frequency f
Output”) and resets the up/down counter directly.
With an external R/C circuitry the IC generates a time base (frequency f
the microcontroller. The watchdog's time window refers to a frequency of
f
A smart watchdog has to ensure that internal problems with its own time base are detected and
do not lead to an undesired status of the complete system. If the RC oscillator stops oscillating a
signal is fed to the OSCERR input after a time-out delay. It resets the up/down counter and dis-
ables the WD-OK output.
Without this reset function the watchdog would freeze in its current status when f
WDC
= 100
OSCERR
f
RCOSC
WDI
RESET
Watchdog Block Diagram
WDI
WDI
detector
Slope
detected by a slope detector resets the binary counter and clocks
Binary counter
Dual MUX
Up/down
counter
Figure
RS-FF
5-2). A missing incoming trigger
Figure
WDI
RC
5-1.
WDC
which is fed to the WDI
WD-OK
(see section “WD-OK
) independent from
RC
4707B–AUTO–10/05
stops.