MAX4822ETP Maxim Integrated Products, MAX4822ETP Datasheet - Page 11

• Manufacturer Part Number: MAX4822ETP
• Description: MOSFET & Power Driver ICs
• Manufacturer: Maxim Integrated Products

Specifications of MAX4822ETP

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Figure 2. 8-Bit Register Map for MAX4823
Figure 4. 3-Wire Serial-Interface Timing Diagram
the MAX4823 device. If the address A0…….A7 is not
00h or 01h, then the outputs and the PSAVE configura-
tion register are not updated. The address is stored in
the shift register only.
While CS is low, the OUT_ outputs always remain in their
previous state. For the MAX4823, drive CS high after 8
bits of data have been shifted in to update the output
state of the MAX4823, and to further inhibit data from
entering the shift register. For the MAX4822, drive CS high
after 16 bits of data have been shifted in to update the
output state of the MAX4822, and to further inhibit data
from entering the shift register. When CS is high, transi-
tions at DIN and SCLK have no effect on the output, and
the first input bit A7 (or D7) is present at DOUT.
Note: Setting D
D
Example: Setting the D
OUT
MSB
N
D
7
to logic 0 turns off output OUT
8
+3.3V/+5V, 8-Channel Relay Drivers with Fast
OUT
D
SCLK
DOUT
OUT_
6
DIN
CS
7
N
OUT
to logic 1 turns on output OUT
D
5
______________________________________________________________________________________
6
2
OUT
= 1 turns OUT
D
4
Recovery Time and Power-Save Mode
5
t
CSS
OUT
t
N+1
DS
D
D7
3
t
DH
4
.
3
on.
OUT
D
2
3
t
CL
N+1
OUT
D
. Setting
1
D6
2
t
CH
OUT
LSB
D
0
1
For the MAX4822, if the number of data bits entered
while CS is low is greater or less than 16, the shift regis-
ter contains only the last 16 bits, regardless of when
they were entered. For the MAX4823, if the number of
data bits entered while CS is low is greater or less than
8, the shift register contains only the last 8 data bits,
regardless of when they were entered.
The parallel interface consists of 3 address bits (A0,
A1, A2) and one level selector bit (LVL). The address
bits determine which output is updated, and the level
bit determines whether the addressed output is
switched on (LVL = high) or off (LVL = low). When CS is
high, the address and level bits have no effect on the
state of the outputs. Driving CS from low to high latches
Figure 3. Register Address Map for MAX4824/MAX4825
High
High
High
High
D1
Low
Low
Low
Low
A2
Parallel Interface (MAX4824/MAX4825)
t
DO
High
High
High
High
Low
Low
Low
Low
A1
D0
t
CSH
High
High
High
High
Low
Low
Low
Low
A0
t
t
ON
OFF
,
t
CSW
OUTPUT
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
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