MAX4824ETP Maxim Integrated Products, MAX4824ETP Datasheet - Page 10

• Manufacturer Part Number: MAX4824ETP
• Description: MOSFET & Power Driver ICs
• Manufacturer: Maxim Integrated Products

Specifications of MAX4824ETP

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

When CS is low (MAX4822/MAX4823 device is select-
ed), data at DIN is clocked into the shift register syn-
chronously with SCLK’s rising edge. Driving CS from
low to high latches the data in the shift register (Figures
5 and 6).
+3.3V/+5V, 8-Channel Relay Drivers with Fast
Recovery Time and Power-Save Mode
Figure 1. 16-Bit Register Map for MAX4822
10
Serial-Input Address Map
Output Control Register—OUT
Note: Setting D
Power-Save Configuration Register—PS (Address= 01h)
Power-Save Configuration Options
Note 1: The time period t
ADDRESS [A7...A0]
______________________________________________________________________________________
PS0
OUT
MSB
MSB
0
0
0
0
1
1
1
1
D
D
X
7
7
00h
01h
8
N
to logic 1 turns on output OUT
PS1
0
0
1
1
0
0
1
1
OUT
D
D
X
6
6
PS
7
Output Control Register—OUTR
is determined by the capacitor connected to PSAVE.
P o w e r - S a ve C o n fi g u r a ti o n
PS2
R
ACTIVE REGISTER
0
1
0
1
0
1
0
1
(Address = 00h)
R e g i s t e r — P S
OUT
D
D
X
5
5
Power-save is disabled (Default Operation)
Power-save is enabled. V
I
Power-save is enabled. V
I
Power-save is enabled. V
I
Power-save is enabled. V
I
Power-save is enabled. V
I
Power-save is enabled. V
I
Power-save is enabled. V
I
OUT
OUT
OUT
OUT
OUT
OUT
OUT
6
_ to be reduced to approximately 30%, typical after t
_ to be reduced to approximately 40%, typical after t
_ to be reduced to approximately 50%, typical after t
_ to be reduced to approximately 60%, typical after t
_ to be reduced to approximately 70%, typical after t
_ to be reduced to approximately 80%, typical after t
_ to be reduced to approximately 90%, typical after t
N+1
. Setting D
OUT
D
D
X
4
4
5
N
to logic 0, turns off OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
DOUT is the output of the shift register. Data appears
on DOUT synchronously with SCLK’s falling edge and
is identical to the data at DIN delayed by eight clock
cycles for the MAX4823, or 16 clock cycles for the
MAX4822. When shifting the input data, A7 is the first
input bit in and out of the shift register for the MAX4822
device. D7 is the first bit in or out of the shift register for
POWER-SAVE CONFIGURATION
set to 70% of V
set to 60% of V
set to 50% of V
set to 40% of V
set to 30% of V
set to 20% of V
set to 10% of V
OUT
D
D
X
3
3
4
CC
CC
CC
CC
CC
CC
CC
N+1
OUT
, typical after t
, typical after t
, typical after t
, typical after t
, typical after t
, typical after t
, typical after t
PS0
D
D
. Example: Setting D
2
2
3
PS
PS
PS
PS
PS
PS
PS
ms.
ms.
ms.
ms.
ms.
ms.
ms.
PS
PS
PS
PS
PS
PS
PS
OUT
PS1
ms (see Note 1), causes
ms (see Note 1), causes
ms (see Note 1), causes
ms (see Note 1), causes
ms (see Note 1), causes
ms (see Note 1), causes
ms (see Note 1), causes
D
D
1
1
2
2
= 1 turns on OUT
OUT
LSB
PS2
LSB
D
D
0
0
1
3
.