DS90C032BTMX/NOPB National Semiconductor, DS90C032BTMX/NOPB Datasheet - Page 3

• Manufacturer Part Number: DS90C032BTMX/NOPB
• Description: IC LINE RCVR LVDS QUAD 16-SOIC
• Manufacturer: National Semiconductor
• Type: Receiverr

Specifications of DS90C032BTMX/NOPB

• Number Of Drivers/receivers: 0/4
• Protocol: RS644
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: *DS90C032BTMX; *DS90C032BTMX/NOPB; DS90C032BTMX

t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Symbol
Symbol
PHLD
PLHD
SKD
SK1
TLH
THL
PHZ
PLZ
PZH
PZL
PHLD
PLHD
SKD
SK1
SK2
TLH
THL
PHZ
PLZ
PZH
PZL
Switching Characteristics
V
Switching Characteristics
V
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground unless otherwise
specified.
Note 3: All typicals are given for: V
Note 4: Generator waveform for all tests unless otherwise specified: f = 1 MHz, Z
Note 5: Channel-to-Channel Skew is defined as the difference between the propagation delay of one channel and that of the others on the same chip with an event
on the inputs.
Note 6: Chip to Chip Skew is defined as the difference between the minimum and maximum specified differential propagation delays.
Note 7: ESD Rating:
Note 8: Output short circuit current (I
exceed maximum junction temperature specification.
Note 9: C
Parameter Measurement Information
CC
CC
HBM (1.5 kΩ, 100 pF) ≥ 2kV
EIAJ (0Ω, 200 pF) ≥ 250V
= +5.0V, T
= +5.0V
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Skew |t
Channel-to-Channel Skew (Note 5)
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
Differential Propagation Delay High to Low
Differential Propagation Delay Low to High
Differential Skew |t
Channel-to-Channel Skew (Note 5)
Chip to Chip Skew (Note 6)
Rise Time
Fall Time
Disable Time High to Z
Disable Time Low to Z
Enable Time Z to High
Enable Time Z to Low
L
includes probe and jig capacitance.
±
A
10%, T
= +25˚C (Notes 3, 4, 9)
A
= −40˚C to +85˚C (Notes 3, 4, 9)
FIGURE 1. Receiver Propagation Delay and Transition Time Test Circuit
PHLD
PHLD
CC
OS
= +5.0V, T
) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not
− t
− t
Parameter
Parameter
PLHD
PLHD
A
|
|
= +25˚C.
3
O
= 50Ω, t
C
V
R
C
C
V
R
C
(Figure 1 and Figure 2)
(Figure 3 and Figure 4)
(Figure 1 and Figure 2)
(Figure 3 and Figure 4)
L
ID
L
L
L
ID
L
L
r
= 5 pF
= 2 kΩ
= 10 pF
= 5 pF
= 2 kΩ
= 10 pF
= 200 mV
= 200 mV
and t
Conditions
Conditions
f
(0%–100%) ≤ 1 ns for R
10099003
IN
Min
Min
1.5
1.5
1.0
1.0
0
0
0
0
and t
r
and t
3.40
3.48
3.40
3.48
0.08
Typ
Typ
0.6
0.5
0.5
0.6
0.5
0.5
80
10
10
10
10
4
4
4
4
f
≤ 6 ns for EN or EN*.
Max
Max
600
5.0
5.0
1.0
2.0
2.0
6.0
6.0
1.2
1.5
5.0
2.5
2.5
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15
15
10
10
20
20
15
15
Units
Units
ns
ns
ps
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns