PIC16F877-20I/PQ Microchip Technology Inc., PIC16F877-20I/PQ Datasheet - Page 118
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PIC16F877-20I/PQ
Manufacturer Part Number
PIC16F877-20I/PQ
Description
44 PIN, 7 KB FLASH, 368 RAM, 33 I/O
Manufacturer
Microchip Technology Inc.
Datasheet
1.PIC16F877-20IPQ.pdf
(218 pages)
Specifications of PIC16F877-20I/PQ
A/d Inputs
8-Channel, 10-Bit
Comparators
2
Cpu Speed
5 MIPS
Eeprom Memory
256 Bytes
Input Output
33
Interface
I2C/SPI/USART
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin PQFP
Programmable Memory
14K Bytes
Ram Size
368 Bytes
Speed
20 MHz
Timers
2-8-bit, 1-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part
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PIC16F87X
11.4
Clearing the GO/DONE bit during a conversion will
abort the current conversion. The A/D result register
pair will NOT be updated with the partially completed
A/D conversion sample. That is, the ADRESH:ADRESL
registers will continue to contain the value of the last
completed conversion (or the last value written to the
ADRESH:ADRESL registers). After the A/D conversion
is aborted, a 2T
FIGURE 11-3:
11.4.1
The ADRESH:ADRESL register pair is the location
where the 10-bit A/D result is loaded at the completion
of the A/D conversion. This register pair is 16-bits wide.
The A/D module gives the flexibility to left or right justify
the 10-bit result in the 16-bit result register. The A/D
FIGURE 11-4:
DS30292C-page 116
A/D Conversions
A/D RESULT REGISTERS
T
CY
Set GO bit
Holding capacitor is disconnected from analog input (typically 100 ns)
7
to T
AD
0000 00
ADRESH
AD
wait is required before the next
Conversion starts
A/D CONVERSION T
A/D RESULT JUSTIFICATION
T
AD
Right Justified
1
2 1 0 7
ADFM = 1
T
AD
b9
2
10-bit Result
T
ADRESL
AD
b8
3
T
AD
b7
AD
4
0
CYCLES
T
AD
b6
10-bit Result
5
T
AD
b5
6
acquisition is started. After this 2T
on the selected channel is automatically started. The
GO/DONE bit can then be set to start the conversion.
In Figure 11-3, after the GO bit is set, the first time seg-
ment has a minimum of T
Format Select bit (ADFM) controls this justification.
Figure 11-4 shows the operation of the A/D result justi-
fication. The extra bits are loaded with ’0’s’. When an
A/D result will not overwrite these locations (A/D dis-
able), these registers may be used as two general
purpose 8-bit registers.
ADRES is loaded
GO bit is cleared
ADIF bit is set
Holding capacitor is connected to analog input
T
AD
b4
Note:
7
7
T
AD
b3
ADRESH
8
The GO/DONE bit should NOT be set in
the same instruction that turns on the A/D.
10-bit Result
T
AD
b2
ADFM = 0
9
Left Justified
T
0 7 6 5
AD
b1
10 T
CY
ADRESL
2001 Microchip Technology Inc.
and a maximum of T
AD
b0
0000 00
11
AD
0
wait, acquisition
AD
.
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