ISP1506BBS-T ST-Ericsson Inc, ISP1506BBS-T Datasheet - Page 48

• Manufacturer Part Number: ISP1506BBS-T
• Description: IC ULPI TRANSCEIVER 24-HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1506BBS-T

• Number Of Drivers/receivers: 1/1
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 29.
Table 30.
ISP1506A_ISP1506B_1
Product data sheet
Bit
7
6
5
4
3
2
1
0
Bit
Symbol
Reset
Access
Symbol
USE_EXT_
VBUS_IND
DRV_VBUS_
EXT
DRV_VBUS
CHRG_VBUS
DISCHRG_
VBUS
DM_PULL
DOWN
DP_PULL
DOWN
ID_PULLUP
OTG Control register (address R = 0Ah to 0Ch, W = 0Ah, S = 0Bh, C = 0Ch) bit description
USB Interrupt Enable Rising Edge register (address R = 0Dh to 0Fh, W = 0Dh, S = 0Eh, C = 0Fh) bit
allocation
10.1.5 USB Interrupt Enable Rising Edge register
R/W/S/C
7
0
The bits in this register enable interrupts and RXCMDs to be sent when the corresponding
bits in the USB Interrupt Status register change from logic 0 to logic 1. By default, all
transitions are enabled.
Description
Use External V
0b — Use the internal OTG comparator (default).
1b — Use the external V
Drive V
external charge pump or a 5 V supply is optional.
0b — Drives V
(default).
1b — Drives V
Drive V
setting DRV_VBUS is optional.
0b — Do not drive V
1b — Drive 5 V on V
Charge V
check that V
have been LOW (SE0) for 2 ms.
0b — Do not charge V
1b — Charge V
Discharge V
an RXCMD indicating that SESS_END has changed from 0 to 1, and then resets this bit to 0 to
stop the discharge.
0b — Do not discharge V
1b — Discharge V
DM Pull Down: Enables the 15 k pull-down resistor on DM.
0b — Pull-down resistor is not connected to DM.
1b — Pull-down resistor is connected to DM (default).
DP Pull Down: Enables the 15 k pull-down resistor on DP.
0b — Pull-down resistor is not connected to DP.
1b — Pull-down resistor is connected to DP (default).
ID Pull Up: Connects a pull-up to the ID line and enables sampling of the ID level. Disabling the ID
line sampler will reduce the PHY power consumption.
0b — Disables sampling of the ID line (default).
1b — Enables sampling of the ID line.
reserved
R/W/S/C
BUS
BUS
6
0
BUS
: Signals the ISP1506 to drive 5 V on V
External: Selects between the internal and external 5 V V
BUS
BUS
: Charges V
BUS
BUS
BUS
BUS
is discharged (see bit DISCHRG_VBUS), and that both the DP and DM data lines
: Discharges V
R/W/S/C
BUS
using the internal charge pump. Also ensures PSW_N is not driven to LOW
using the external charge pump or the 5 V supply. Drives PSW_N to LOW.
.
Indicator: Informs the PHY to use an external V
BUS
BUS
5
0
.
BUS
.
(default).
BUS
BUS
BUS
Rev. 01 — 30 May 2007
Table 30
(default).
valid indicator signal input from the FAULT pin.
through a resistor. Used for the V
(default).
ID_GND_R
BUS
R/W/S/C
through a resistor. If the link sets this bit to logic 1, it waits for
4
1
shows the bit allocation of the register.
R/W/S/C
END_R
SESS_
3
1
ISP1506A; ISP1506B
BUS
. If DRV_VBUS_EXT is set to logic 1, then
VALID_R
R/W/S/C
SESS_
BUS
ULPI HS USB OTG transceiver
2
1
pulsing SRP. The link must first
BUS
BUS
overcurrent indicator.
VALID_R
R/W/S/C
supply. Using an
VBUS_
1
1
© NXP B.V. 2007. All rights reserved.
DISCON_R
R/W/S/C
HOST_
0
1
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