DSPIC30F6013A-30I/PT Microchip Technology Inc., DSPIC30F6013A-30I/PT Datasheet - Page 129
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DSPIC30F6013A-30I/PT
Manufacturer Part Number
DSPIC30F6013A-30I/PT
Description
DSP, 16-Bit, 132 KB Flash, 6KB RAM, 68 I/O, TQFP-80
Manufacturer
Microchip Technology Inc.
Type
DSPr
Datasheet
1.DSPIC30F6012A-30IPT.pdf
(238 pages)
Specifications of DSPIC30F6013A-30I/PT
A/d Inputs
16-Channels, 12-Bit
Cpu Speed
30 MIPS
Eeprom Memory
2K Bytes
Input Output
68
Interface
CAN, I2C, SPI, UART/USART
Ios
68
Memory Type
Flash
Number Of Bits
16
Package Type
80-pin TQFP
Programmable Memory
132K Bytes
Ram Size
6K Bytes
Timers
5-16-bit, 2-32-bit
Voltage, Range
2.5-5.5
Lead Free Status / Rohs Status
RoHS Compliant part
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18.3.7
The DCI module has a dedicated 12-bit time base that
produces the bit clock. The bit clock rate (period) is set
by writing a non-zero 12-bit value to the BCG<11:0>
control bits in the DCICON3 SFR.
When the BCG<11:0> bits are set to zero, the bit clock
will be disabled. If the BCG<11:0> bits are set to a non-
zero value, the bit clock generator is enabled. These
bits should be set to ‘0’ and the CSCKD bit set to ‘1’ if
the serial clock for the DCI is received from an external
device.
The formula for the bit clock frequency is given in
Equation 18-2.
TABLE 18-1:
© 2006 Microchip Technology Inc.
Note 1: When the CSCK signal is applied externally (CSCKD = 1), the external clock high and low times must meet
F
S
44.1
(KHz)
12
32
48
8
2: When the CSCK signal is applied externally (CSCKD = 1), the BCG<11:0> bits have no effect on the
BIT CLOCK GENERATOR
the device timing requirements.
operation of the DCI module.
DEVICE FREQUENCIES FOR COMMON CODEC CSCK FREQUENCIES
F
dsPIC30F6011A/6012A/6013A/6014A
CSCK
256
256
32
32
64
/F
S
F
CSCK
1.4112
2.048
3.072
1.024
3.072
(MHz)
Preliminary
(1)
F
OSC
5.6448
8.192
6.144
8.192
6.144
EQUATION 18-2:
The required bit clock frequency will be determined by
the system sampling rate and frame size. Typical bit
clock frequencies range from 16x to 512x the converter
sample rate depending on the data converter and the
communication protocol that is used.
To achieve bit clock frequencies associated with com-
mon audio sampling rates, the user will need to select
a crystal frequency that has an ‘even’ binary value.
Examples of such crystal frequencies are listed in
Table 18-1.
(MH
Z
)
F
PLL
BCK
16
4
8
8
8
=
BIT CLOCK FREQUENCY
2 (BCG + 1)
•
F
CY
F
CY
11.2896
12.288
16.384
24.576
8.192
(MIPS)
DS70143C-page 127
BCG
1
1
7
3
3
(2)
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