ISP1302HN-T ST-Ericsson Inc, ISP1302HN-T Datasheet - Page 60

• Manufacturer Part Number: ISP1302HN-T
• Description: IC USB OTG TRANSCEIVER 24HVQFN
• Manufacturer: ST-Ericsson Inc
• Type: Transceiverr

Specifications of ISP1302HN-T

• Number Of Drivers/receivers: 1/1
• Protocol: USB 2.0
• Voltage - Supply: 3 V ~ 4.5 V
• Mounting Type: Surface Mount
• Package / Case: 24-VQFN Exposed Pad, 24-HVQFN, 24-SQFN, 24-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. ISP1302 power modes summary . . . . . . . . . . .18
Table 11. ISP1302 pin states in disable and isolate
Table 12. USB functional modes: I/O values . . . . . . . . . .19
Table 13. Summary of device operating modes . . . . . . .21
Table 14. Transparent general-purpose buffer mode . . . .21
Table 15. Register overview . . . . . . . . . . . . . . . . . . . . . .22
Table 16. Vendor ID register (address R = 00h to 01h)
Table 17. Product ID register (address R = 02h to 03h)
Table 18. Version ID register (address R = 14h to 15h)
Table 19. Version ID register (address R = 14h to 15h)
Table 20. Mode Control 1 register (address S = 04h,
Table 21. Mode Control 1 register (address S = 04h,
Table 22. Mode Control 2 register (address S = 12h,
Table 23. Mode Control 2 register (address S = 12h,
Table 24. Audio Control register (address S = 16h,
Table 25. Audio Control register (address S = 16h,
Table 26. OTG Control register (address S = 06h,
Table 27. OTG Control register (address S = 06h,
Table 28. Misc Control register (address S = 18h,
Table 29. Misc Control register (address S = 18h,
Table 30. Carkit Control register (address S = 1Ah,
Table 31. Carkit Control register (address S = 1Ah,
ISP1302_1
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
ID pin status for various applications . . . . . . . . .9
ID pull-down control . . . . . . . . . . . . . . . . . . . . .10
Transceiver driver operating setting . . . . . . . . .15
USB functional mode: transmit operation . . . .15
Differential receiver operation settings . . . . . . .15
USB functional mode: receive operation . . . . .15
Possible combinations of I
and the PSW polarity . . . . . . . . . . . . . . . . . . . .17
modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .23
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
C = 05h) bit allocation . . . . . . . . . . . . . . . . . . .24
C = 05h) bit description . . . . . . . . . . . . . . . . . .24
C = 13h) bit allocation . . . . . . . . . . . . . . . . . . .24
C = 13h) bit description . . . . . . . . . . . . . . . . . .25
C = 17h) bit allocation . . . . . . . . . . . . . . . . . . .25
C = 17h) bit description . . . . . . . . . . . . . . . . . .25
C = 07h) bit allocation . . . . . . . . . . . . . . . . . . .25
C = 07h) bit description . . . . . . . . . . . . . . . . . .26
C = 19h) bit allocation . . . . . . . . . . . . . . . . . . .26
C = 19h) bit description . . . . . . . . . . . . . . . . . .26
C = 1Bh) bit allocation . . . . . . . . . . . . . . . . . . .27
2
C-bus address
Rev. 01 — 24 May 2007
Table 32. Transmit Positive Width register (address
Table 33. Transmit Negative Width register (address
Table 34. Receive Polarity Recovery register (address
Table 35. Carkit Interrupt Delay register (address
Table 36. OTG Status register (address R = 10h) bit
Table 37. OTG Status register (address R = 10h) bit
Table 38. Interrupt Source register (address R = 08h)
Table 39. Interrupt Source register (address R = 08h)
Table 40. Interrupt Latch register (address S = 0Ah,
Table 41. Interrupt Latch register (address S = 0Ah,
Table 42. Interrupt Enable Low register (address
Table 43. Interrupt Enable Low register (address
Table 44. Interrupt Enable High register (address
Table 45. Interrupt Enable High register (address
Table 46. I
Table 47. I
Table 48. I
Table 49. Transfer format description for a one-byte
Table 50. Transfer format description for a
Table 51. Transfer format description for current
Table 52. Transfer format description for a single-byte
Table 53. Transfer format description for a
Table 54. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 55. Recommended operating conditions . . . . . . . . 39
Table 56. Static characteristics: supply pins . . . . . . . . . . 40
Table 57. Static characteristics: digital pins . . . . . . . . . . 41
Table 58. Static characteristics: analog I/O pins
C = 1Bh) bit description . . . . . . . . . . . . . . . . . . 27
R/W = 1Ch) bit description . . . . . . . . . . . . . . . 28
R/W = 1Dh) bit description . . . . . . . . . . . . . . . 28
R/W = 1Eh) bit description . . . . . . . . . . . . . . . 28
R/W = 1Fh) bit description . . . . . . . . . . . . . . . 28
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 29
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 30
C = 0Bh) bit allocation . . . . . . . . . . . . . . . . . . . 31
C = 0Bh) bit description . . . . . . . . . . . . . . . . . . 31
S = 0Ch, C = 0Dh) bit allocation . . . . . . . . . . . 31
S = 0Ch, C = 0Dh) bit description . . . . . . . . . . 32
S = 0Eh, C = 0Fh) bit allocation . . . . . . . . . . . 32
S = 0Eh, C = 0Fh) bit description . . . . . . . . . . 32
write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
multiple-byte write . . . . . . . . . . . . . . . . . . . . . . 34
address read . . . . . . . . . . . . . . . . . . . . . . . . . . 36
read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
multiple-byte read . . . . . . . . . . . . . . . . . . . . . . 36
DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
USB OTG transceiver with carkit support
2
2
2
C-bus byte transfer format . . . . . . . . . . . . . . 33
C-bus slave address bit allocation . . . . . . . . 33
C-bus slave address bit description . . . . . . . 34
© NXP B.V. 2007. All rights reserved.
ISP1302
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