PIC18F4550-I/ML Microchip Technology Inc., PIC18F4550-I/ML Datasheet - Page 177

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PIC18F4550-I/ML

Manufacturer Part Number
PIC18F4550-I/ML
Description
44 PIN, 32 KB FLASH, 2048 RAM, FS-USB 2.0
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F4550-I/ML

A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
12 MIPS
Eeprom Memory
256 Bytes
Input Output
34
Interface
I2C/SPI/UART/USART/USB
Memory Type
Flash
Number Of Bits
8
Package Type
44-pin QFN
Programmable Memory
32K Bytes
Ram Size
2K Bytes
Speed
48 MHz
Timers
1-8-bit, 3-16-bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device
REGISTER 16-3:
© 2006 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5-3
bit 2-0
Note 1:
R/W-0
ADFM
If the A/D F
clock starts. This allows the SLEEP instruction to be executed before starting a conversion.
ADFM: A/D Result Format Select bit
1 = Right justified
0 = Left justified
Unimplemented: Read as ‘0’
ACQT2:ACQT0: A/D Acquisition Time Select bits
111 = 20 T
110 = 16 T
101 = 12 T
100 = 8 T
011 = 6 T
010 = 4 T
001 = 2 T
000 = 0 T
ADCS2:ADCS0: A/D Conversion Clock Select bits
111 = F
110 = F
101 = F
100 = F
011 = F
010 = F
001 = F
000 = F
U-0
ADCON2: A/D CONTROL REGISTER 2
RC
RC
OSC
OSC
OSC
RC
OSC
OSC
OSC
AD
AD
AD
AD
AD (1)
clock source is selected, a delay of one T
AD
AD
AD
(clock derived from A/D RC oscillator)
(clock derived from A/D RC oscillator)
/64
/16
/4
/32
/8
/2
W = Writable bit
‘1’ = Bit is set
ACQT2
R/W-0
Advance Information
ACQT1
R/W-0
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ACQT0
R/W-0
(1)
(1)
CY
(instruction cycle) is added before the A/D
PIC18F2450/4450
ADCS2
R/W-0
x = Bit is unknown
ADCS1
R/W-0
DS39760A-page 175
ADCS0
R/W-0
bit 0

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