PIC18F4620-E/P Microchip Technology Inc., PIC18F4620-E/P Datasheet - Page 149

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PIC18F4620-E/P

Manufacturer Part Number
PIC18F4620-E/P
Description
40 Pin, 64 KB Flash, 3968 RAM, 36 I/O
Manufacturer
Microchip Technology Inc.
Datasheet

Specifications of PIC18F4620-E/P

A/d Inputs
13-Channel, 10-Bit
Comparators
2
Cpu Speed
10 MIPS
Eeprom Memory
1024 Bytes
Input Output
36
Interface
SPI/I2C/USART
Memory Type
Flash
Number Of Bits
8
Package Type
40-pin PDIP
Programmable Memory
64K Bytes
Ram Size
4K Bytes
Speed
40 MHz
Timers
1-8 bit, 3-16 bit
Voltage, Range
2-5.5 V
Lead Free Status / Rohs Status
RoHS Compliant part Electrostatic Device

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Quantity
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Part Number:
PIC18F4620-E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
16.0
In PIC18F4525/4620 devices, CCP1 is implemented
as a standard CCP module with Enhanced PWM
capabilities. These include the provision for 2 or 4
output channels, user selectable polarity, dead-band
control and automatic shutdown and restart. The
REGISTER 16-1:
 2004 Microchip Technology Inc.
Note:
ENHANCED CAPTURE/
COMPARE/PWM (ECCP)
MODULE
The ECCP module is implemented only in
40/44-pin devices.
bit 7-6
bit 5-4
bit 3-0
CCP1CON REGISTER (ECCP1 MODULE, 40/44-PIN DEVICES)
Legend:
R = Readable bit
-n = Value at POR
bit 7
P1M1:P1M0: Enhanced PWM Output Configuration bits
If CCP1M3:CCP1M2 = 00, 01, 10:
xx = P1A assigned as Capture/Compare input/output; P1B, P1C, P1D assigned as port pins
If CCP1M3:CCP1M2 = 11:
00 = Single output: P1A modulated; P1B, P1C, P1D assigned as port pins
01 = Full-bridge output forward: P1D modulated; P1A active; P1B, P1C inactive
10 = Half-bridge output: P1A, P1B modulated with dead-band control; P1C, P1D assigned
11 = Full-bridge output reverse: P1B modulated; P1C active; P1A, P1D inactive
DC1B1:DC1B0: PWM Duty Cycle bit 1 and bit 0
Capture mode:
Unused.
Compare mode:
Unused.
PWM mode:
These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are
found in CCPR1L.
CCP1M3:CCP1M0: Enhanced CCP Mode Select bits
0000 = Capture/Compare/PWM off (resets ECCP module)
0001 = Reserved
0010 = Compare mode, toggle output on match
0011 = Capture mode
0100 = Capture mode, every falling edge
0101 = Capture mode, every rising edge
0110 = Capture mode, every 4th rising edge
0111 = Capture mode, every 16th rising edge
1000 = Compare mode, initialize CCP1 pin low, set output on compare match (set CCP1IF)
1001 = Compare mode, initialize CCP1 pin high, clear output on compare match (set CCP1IF)
1010 = Compare mode, generate software interrupt only, CCP1 pin reverts to I/O state
1011 = Compare mode, trigger special event (ECCP resets TMR1 or TMR3, sets CC1IF bit)
1100 = PWM mode; P1A, P1C active-high; P1B, P1D active-high
1101 = PWM mode; P1A, P1C active-high; P1B, P1D active-low
1110 = PWM mode; P1A, P1C active-low; P1B, P1D active-high
1111 = PWM mode; P1A, P1C active-low; P1B, P1D active-low
R/W-0
P1M1
as port pins
R/W-0
P1M0
PIC18F2525/2620/4525/4620
DC1B1
R/W-0
W = Writable bit
‘1’ = Bit is set
Preliminary
DC1B0
R/W-0
Enhanced features are discussed in detail in
Section 16.4 “Enhanced PWM Mode”. Capture,
Compare and single-output PWM functions of the
ECCP module are the same as described for the
standard CCP module.
The control register for the Enhanced CCP module is
shown in Register 16-1. It differs from the CCPxCON
registers in PIC18F2525/2620 devices in that the two
Most Significant bits are implemented to control PWM
functionality.
CCP1M3
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0
CCP1M2
R/W-0
x = Bit is unknown
CCP1M1
R/W-0
DS39626B-page 147
CCP1M0
R/W-0
bit 0

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